Patents Represented by Attorney Fish & Neave IP Group Ropes & Gray LLP
  • Patent number: 7242012
    Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: July 10, 2007
    Assignee: Elm Technology Corporation
    Inventor: Glenn J Leedy
  • Patent number: 7241662
    Abstract: A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that can result in the exposure of the silicon corners. The exposure of a silicon corner may increase thinning of a gate oxide at the field edge. This causes variability and unreliability in the device. The dielectric is not removed from a device until the device is ready for processing. That is, the dielectric remains on a device until the growing of a gate oxide on that device has begun. This reduces the exposure of the silicon corner. Hedges that result may be removed by exposing a trench in the field oxide at the hedge.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: July 10, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Graham R Wolstenholme, Mark A Helm
  • Patent number: 7241989
    Abstract: Disclosed herein are systems, methods and apparatus, for detection and identification of analytes in a volatilized or volatilizable sample, using the mobility-based signature that is produced when the volatilized sample is passed through an ion mobility based analyzer.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: July 10, 2007
    Assignee: Sionex Corp.
    Inventors: Raanan A. Miller, Erkinjon G. Nazarov, Angela Zapata, Cristina E. Davis, Gary A. Eiceman, Anthony D. Bashall
  • Patent number: 7242221
    Abstract: Programmable logic device circuitry for receiving and/or transmitting a differential signal includes controllable invert circuitry that effectively reverses the polarity of the differential signal. The controllable invert circuitry operates on a single-ended (non-differential) signal that has either been derived from a differential input signal or from which a differential output signal will be derived.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: July 10, 2007
    Assignee: Altera Corporation
    Inventors: Tim T Hoang, Sergey Y Shumarayev, Wilson Wong, Simardeep Maangat
  • Patent number: 7243329
    Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: July 10, 2007
    Assignee: Altera Corporation
    Inventors: Kar Keng Chua, Sammy Cheung
  • Patent number: 7243315
    Abstract: As part of a process for producing a structured ASIC that is functionally equivalent to an FPGA that has been programmed to perform a user's logic design, a compilation of that design that has been prepared for ASIC implementation is converted to a physical layout of the structured ASIC. The production of this physical layout honors timing constraints supplied by the user, and also preserves functional equivalence to the reference programmed FPGA. The structured ASIC can be manufactured from the physical layout produced.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: July 10, 2007
    Assignee: Altera Corporation
    Inventors: Kim Pin Tan, Kar Keng Chua
  • Patent number: 7242774
    Abstract: A quantum cryptography system [100] may include a transmitter [110] configured to generate entangled first and second photons, modulate and detect the first photon, and transmit detection information and the second photon. The system [100] may also include a receiver [160] configured to modulate the second photon. The receiver [160] may also be configured to detect the second photon based on the detection information.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: July 10, 2007
    Assignee: BBN Technologies Corp.
    Inventors: Brig Barnum Elliott, John D. Schlafer, David Spencer Pearson
  • Patent number: 7239849
    Abstract: Possible deficiencies of a communication link are detected and automatically counteracted, at least to some degree. The deficiencies addressed can include phase shift and attenuation compensation. The counter-action can include adjustment of pre-emphasis given a signal applied to the communication link and/or adjustment of equalization given a signal received from the communication link.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: July 3, 2007
    Assignee: Altera Corporation
    Inventors: Bill Bereza, Mashkoor Baig, Shoujun Wang, Haitao Mei, Tad Kwasniewski
  • Patent number: 7239986
    Abstract: Methods and apparatus for classifying or predicting the classes for samples based on gene expression are described. Also described are methods and apparatus for ascertaining or discovering new, previously unknown classes based on gene expression.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: July 3, 2007
    Assignees: Whitehead Institute for Biomedical Research, Dana-Farber Cancer Institute, Inc.
    Inventors: Todd R. Golub, Eric S. Lander, Jill Mesirov, Donna Slonim, Pablo Tamayo
  • Patent number: 7240133
    Abstract: A data converter for a padded protocol interface performs, on a first data sample, decoding operations requiring data from second and third data samples, while buffering the second data sample without buffering the third data sample. A state machine controlling the decoding operation waits an additional clock cycle, until the second sample has become the current sample and the third sample has become the second sample and thus is available.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: July 3, 2007
    Assignee: Altera Corporation
    Inventor: Ning Xue
  • Patent number: 7239719
    Abstract: A system and method can detect and track targets in a scene of interest. Interframe differencing can be performed on sequential pairs of images of the scene and a Bayesian model analyzer can obtain an interframe difference density function. The interframe difference density function can be partitioned into static and mobile regimes to provide an objective function. A tracking module can construct a level set and geodesic active contours can be determined for the targets. An adaptive control can apply a spatial transformation and level set perturbation to the geodesic contours to oscillate the contours such that the level set can drop to a lower energy level. The expanded contour can be fed back for use in processing subsequent interframe differences. Target motion analysis data, such as bearing and bearing rate data, can be extracted from the geodesic active contours by applying geometric based transformations on the curve's coordinates.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: July 3, 2007
    Assignee: BBN Technologies Corp.
    Inventors: Kevin Paul Bongiovanni, Paul Patrick Audi, Christopher S. Fortin, Kenneth J. McPhillips
  • Patent number: 7239798
    Abstract: Digital compressed codes, associated with advertisements enable a user to selectively record additional information, which would be broadcast on a television channel at a later time. The advertisement could be print advertisement or broadcast advertisement on television or radio. The user enters the digital code (I code) associated with an advertisement into a unit with a decoding means which automatically converts the code into CTL (channel, time and length). The unit within a twenty four hour period activates a VCR to record information on the television channel at the right time for the proper length of time. The decoded channel, time and length information can be communicated directly to a VCR and used by the VCR directly to automatically activate the VCR to record a given television information broadcast corresponding to the communicated channel, time and length.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: July 3, 2007
    Assignee: Gemstar Development Corporation
    Inventors: Henry C. Yuen, Daniel S. Kwoh
  • Patent number: 7239180
    Abstract: Programmable logic devices, such as field programmable gate arrays, may have input/output (I/O) circuitry that can be programmed for either differential or single-ended signaling. I/O pins coupled to such programmable I/O circuitry typically have high parasitic input pin capacitance during differential signaling. I/O pins may also have high parasitic input pin inductance. Additional impedance circuit elements such as capacitive or inductive devices are coupled in the programmable I/O circuitry to produce a compensatory impedance that reduces, if not substantially eliminates, the effects of the parasitic input pin capacitance and/or inductance during differential signaling.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: July 3, 2007
    Assignee: Altera Corporation
    Inventor: Sergey Y Shumarayev
  • Patent number: 7236018
    Abstract: The present invention relates to a programmable low-voltage differential signaling (LVDS) output driver. The programmable LVDS output driver may include circuitry for tri-stating the output to allow several programmable LVDS output drivers to be coupled to a single receiver. The programmable LVDS output driver may also include programmable current sources for varying the output current, as well as providing additional current to circuitry within the driver (e.g., impedance circuitry). The programmable LVDS output driver may also include an impedance circuit for adjusting the output impedance of the output driver, while only diverting a small amount of source current. The current diverted by the impedance circuit may be compensated for by increasing the source current from the programmable current sources. The programmable LVDS output driver may also include pre-emphasis circuitry for boosting the edge rates of output signals.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: June 26, 2007
    Assignee: Altera Corporation
    Inventors: Bonnie Wang, Chiakang Sung, Khai Nguyen
  • Patent number: 7235383
    Abstract: Disclosed is a method for identifying substances that alter the interaction of a presenilin protein with a presenilin-binding protein, including contacting at least the interacting domain of a presenilin protein to a presenilin-binding protein in the presence of a test substance, and measuring the interaction of the presenilin protein and the presenilin-binding protein. Also disclosed is method for identifying substances that modulate the nuclear translocation of an armadillo protein, including providing a culture of cells that express the armadillo protein and a mutant presenilin protein, or a functional fragment thereof that binds an armadillo protein; contacting the culture with a test substance; inducing nuclear translocation of the armadillo protein in the cells; and measuring levels of nuclear armadillo protein as compared to a control as an indication of modulatory activity of the test substance.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: June 26, 2007
    Assignee: The Governing Council of the University of Toronto
    Inventors: Peter H. St. George-hyslop, Paul E. Fraser
  • Patent number: 7235043
    Abstract: A system for implanting an implant and method thereof is disclosed. In general overview, the system includes an implant, an envelope enclosing the implant, a delivery assembly and an attachment piece for attaching the envelope or implant to the delivery assembly. The envelope may include a drug coating, positioning aids, and means to ease envelope removal. In one embodiment, the delivery assembly is employed for implant and/or envelope delivery inside the patient's body. In another embodiment, the delivery assembly and an attachment piece are employed to deliver the implant or the envelope inside the patient's body.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: June 26, 2007
    Assignee: Boston Scientific Scimed Inc.
    Inventors: Barry N. Gellman, Armand Morin, Jozef Slanda, Richard C. Tah
  • Patent number: 7236597
    Abstract: Methods, apparatus, and systems are provided for distributing a key between nodes. The nodes are provided separate links for carrying messages versus keying information or material. The links for carrying messages couple the nodes to a messaging network, such as the Internet. In addition, the nodes are coupled together in a key distribution network by specialized links for carrying keying information or material. The links for keying information or material are configured to ensure the security of the keying information or material. The nodes that neighbor each other in the key distribution network establish respective pairwise keys. Once the pairwise keys are established, a set of non-neighboring nodes establish a shared key by communicating a sequence of bits through the messaging network. In order to ensure the security of the sequence of bits, the sequence of bits is encrypted based on the respective pairwise keys of neighboring nodes as it is forwarded in messages through the messaging network.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: June 26, 2007
    Assignee: BBN Technologies Corp.
    Inventors: Brig Barnum Elliott, David Spencer Pearson
  • Patent number: 7235488
    Abstract: Chemical-mechanical planarization (CMP) apparatus and methods for detecting polishing pad properties using ultrasonic imaging is presented. An ultrasonic probe assembly transmits ultrasonic signals onto the surface of a polishing pad during a CMP process. Reflected ultrasonic signals are collected and analyzed to monitor polishing pad properties in real-time. This allows CMP process adjustments to be made during the CMP process.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: June 26, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Jason B Elledge
  • Patent number: D545586
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: July 3, 2007
    Assignee: DeCoro, Limited
    Inventor: Luca Ricci
  • Patent number: D546092
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: July 10, 2007
    Assignee: DeCoro Limited
    Inventor: Luca Ricci