Patents Represented by Law Firm Fletcher, Yoder & Edwards
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Patent number: 5998244Abstract: A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer process, small pores are formed in the silicon nitride to expose a portion of the polysilicon plugs. A chalcogenide material is disposed in the pores by depositing a layer of chalcogenide material on the silicon nitride layer and planarizing the chalcogenide layer to the silicon nitride layer using CMP. A layer of TiN is next deposited over the plugs, followed by a metallization layer. The TiN and metallization layers are then masked and etched to define memory cell areas.Type: GrantFiled: August 22, 1996Date of Patent: December 7, 1999Assignee: Micron Technology, Inc.Inventors: Graham R. Wolstenholme, Fernando Gonzalez, Russell C. Zahorik
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Patent number: 5891791Abstract: A method for forming a P-type region in a semiconducting crystalline substrate by ion implantation is disclosed, wherein the implant specie is an ionic molecule that contains titanium and boron.Type: GrantFiled: May 27, 1997Date of Patent: April 6, 1999Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Mohammed Anjum
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Patent number: 5872052Abstract: A planarization process for filling spaces between patterned metal features formed over a surface of a semiconductor substrate. The patterned metal features are preferably coated with a dielectric barrier. The dielectric barrier is coated with an material that expands during oxidation or nitridization to a thickness about half the depth of the space between metallized features. The layer is then plasma oxidized using an RF or ECR plasma at low temperature with an oxygen ambient. Alternatively, the layer is plasma nitridized at low temperature. The plasma oxidation or nitridization is continued until the expandable material is converted to a dielectric and has expanded to fill the space between patterned metal features. Optionally, the process can be followed by a mechanical or chemical mechanical planarization step.Type: GrantFiled: February 12, 1996Date of Patent: February 16, 1999Assignee: Micron Technology, Inc.Inventor: Ravi Iyer
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Patent number: 5862873Abstract: A preform element, for example for use as a cutting element on a rotary drag-type drill bit, includes a facing table of superhard material having a front face and a rear face bonded to the front face of a substrate which is less hard than the superhard material. The rear face of the facing table comprises a surface formed with a plurality of spaced protuberances and a plurality of spaced sockets, and the front face of the substrate comprises a surface which is bonded to the surface of the facing table and is formed with a plurality of spaced protuberances which are bonded within said sockets in the facing table, and a plurality of spaced sockets within which are bonded said protuberances on the facing table.Type: GrantFiled: March 15, 1996Date of Patent: January 26, 1999Assignee: Camco Drilling Group LimitedInventors: Terry R. Matthias, Alex Newton, Daniel J. Sarik
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Patent number: 5851734Abstract: A process for forming patterns in resist material on a semiconductor wafer that uses two masks to define a pattern instead of a single conventional mask to define the pattern. The present invention realizes better process latitude and resolution for a given feature size than did the prior art.Type: GrantFiled: March 26, 1996Date of Patent: December 22, 1998Assignee: Micron Technology, Inc.Inventor: Christophe Pierrat
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Patent number: 5851882Abstract: A cost-competitive, dense, CMOS compatible ZPROM memory array design and method of manufacture is disclosed. The method of manufacture includes a novel method for forming extremely thin diodes and thin strips of other materials such as conductors by using oxide spacers as an etching mask.Type: GrantFiled: May 6, 1996Date of Patent: December 22, 1998Assignee: Micron Technology, Inc.Inventor: Steven T. Harshfield
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Patent number: 5852571Abstract: A ferroelectric memory device has a folded bit line architecture. The ferroelectric memory device may include a selectable upper even memory cell connected to an upper even bit line, a sense amplifier having a first input and a second input; control circuitry operable to connect an upper odd bit line to a lower odd bit line at the first input of the sense amplifier, to connect the upper even bit line to the second input of the sense amplifier, and to isolate a lower even bit line from the second input of the sense amplifier; and a selectable lower odd reference cell, connected to the lower odd bit line.Type: GrantFiled: March 14, 1997Date of Patent: December 22, 1998Assignee: Micron Technology, Inc.Inventor: Wayne I. Kinney
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Patent number: 5851704Abstract: The present invention provides a method and apparatus of fabricating photomasks. The photomasks may be fabricated from a photomask blank structure having multiple layers. Upon patterning of these multiple layers by standard photolithographic processes, a photomask is created which is capable of phase-shifting incident light by various degrees, which may be 0.degree., 60.degree., 120.degree., and 180.degree..Type: GrantFiled: December 9, 1996Date of Patent: December 22, 1998Assignee: Micron Technology, Inc.Inventor: Christophe Pierrat
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Patent number: 5849628Abstract: A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process.Type: GrantFiled: December 9, 1996Date of Patent: December 15, 1998Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Trung T. Doan
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Patent number: 5847439Abstract: The invention proposes methods for producing integrated circuits wherein the dielectric constant between closely spaced and adjacent metal lines is approaching 1. One method of the invention uses low-melting-point dielectric to form a barrier form a void between conductive lines. Another method of the invention uses sidewall film to form a similar barrier.Type: GrantFiled: July 9, 1996Date of Patent: December 8, 1998Assignee: Micron Technology, Inc.Inventor: Alan R. Reinberg
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Patent number: 5839525Abstract: A roller cone or drag-type drill bit for use in drilling subsurface formations, especially useful for directional drilling, has a bit body with a shank portion for connection to a drill string, and a crown portion. Breaker slots are formed in the bit body at or immediately adjacent to the intersection of the crown portion and the shank portion. This location of the breaker slots allows the drill bit to be relatively shorter than comparable prior art bits with the breaker slots formed in the shank portion. The shorter length permits the present drill bit to be more easily steered in directional drilling applications.Type: GrantFiled: December 23, 1996Date of Patent: November 24, 1998Assignee: Camco International Inc.Inventors: Carl M. Hoffmaster, Tim P. Beaton, Keith Terry
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Patent number: 5841150Abstract: The invention provides a vertically oriented diode for use in delivering large amounts of current to a variable resistance element in a multi-state memory cell. The vertical diode is disposed in a diode container extending downwardly from the top of a tall oxide stack into a deep trench in single crystal silicon. The diode is formed of a combination of single crystal and/or polycrystalline silicon layers disposed vertically inside the diode container. The memory element is formed above the diode to complete a memory cell. The vertical construction of the diode provides a large diode surface area capable of generating a very large current flow through the memory element, as is required for programming. In this way, a highly effective diode can be created for delivering a large current without requiring the substrate surface space normally associated with such large diodes.Type: GrantFiled: February 12, 1997Date of Patent: November 24, 1998Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Ray Turi
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Patent number: 5838445Abstract: A method for monitoring surface roughness by applying a controlled amount of liquid onto a specimen surface to form a liquid protrusion. The diameter or area of the a liquid protrusion is measured and correlated to surface roughness. In an alternative embodiment, the contact angle between the specimen surface and the liquid protrusion is measured. Surface roughness is computed from the contact angle measurement and several known physical constants of the liquid and specimen surface.Type: GrantFiled: February 21, 1997Date of Patent: November 17, 1998Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Guy Hudson
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Patent number: 5837564Abstract: A method of fabricating a chalcogenide memory cell wherein a layer of chalcogenide material is deposited in an amorphous state. The layer of amorphous chalcogenide material is then etched to its final geometry while maintaining its amorphous structure. The final geometry of the chalcogenide material is then annealed thereby transforming it to a crystalline form.Type: GrantFiled: November 1, 1995Date of Patent: November 17, 1998Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Alan R. Reinberg
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Patent number: 5831378Abstract: A field emitter display having reduced surface leakage comprising at least one emitter tip surrounded by a dielectric region. The dielectric region is formed of a composite of insulative layers, at least one of which has fins extending toward the emitter tip. A conductive gate, for extracting electrons from the emitter tip, is disposed superjacent the dielectric region. The fins increase the length of the path that leaked electrical charge travels before impacting the gate.Type: GrantFiled: August 25, 1997Date of Patent: November 3, 1998Assignee: Micron Technology, Inc.Inventors: J. Brett Rolfson, Kevin Tjaden
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Patent number: 5830077Abstract: A device for assisting a golfer in improving his or her golf swing. The device includes an impact detector mounted to the club head of a golf club. The impact detector provides an instantaneous visual or audible indicator of when a predetermined area, e.g., the "sweet spot", of the club head face strikes the golf ball.Type: GrantFiled: June 13, 1997Date of Patent: November 3, 1998Inventor: Edward Q. Yavitz
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Patent number: 5831276Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.Type: GrantFiled: July 22, 1996Date of Patent: November 3, 1998Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Raymond A. Turi, Graham R. Wolstenholme, Charles L. Ingalls
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Patent number: 5819860Abstract: A rotary drill bit for use in drilling holes in subsurface formations comprises a bit body having a leading face and a gauge region, a number of blades formed on the leading face of the bit and extending outwardly away from the axis of the bit so as to define between the blades a number of fluid channels leading towards the gauge region, a number of cutting elements mounted side-by-side along each blade, and a number of nozzles in the bit body for supplying drilling fluid to the fluid channels for cleaning and cooling the cutting elements. In at least one of the fluid channels, adjacent the gauge region, is an opening into an enclosed passage which passes internally through the bit body to an outlet which, in use, communicates with the annulus between the drill string and the wall of the borehole being drilled. The portion of the gauge region outwardly of the opening comprises a bearing surface which, in use bears against the wall of the bore hole and extends across the width of the channel.Type: GrantFiled: April 16, 1997Date of Patent: October 13, 1998Assignee: Camco International Inc.Inventors: Alex Newton, Steven Taylor, Andrew Murdock, John M. Clegg
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Patent number: 5820624Abstract: A system for treating vision disorders is disclosed. The system includes a heating device able to heat predetermined areas of the corneal tissue of an eye. The energy for heating is typically generated in the form of laser light or infrared that cause the tissue at that predetermined area to heat and shrink. The shrinkage shifts a plug or portion of the cornea with respect to the remainder of the eye to change the shape of the corneal surface and correct the problematic refractive error. A heat absorption modifier is used to avoid damage to the epithelial layer as energy is passed therethrough.Type: GrantFiled: May 7, 1997Date of Patent: October 13, 1998Assignee: Quadrivium, L.L.C.Inventor: Edward Q. Yavitz
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Patent number: RE36325Abstract: A leadframe interconnect package is tape automated bond (TAB) bonded to circuitry on the chip and which provides a circuit connection for subsequent connection to a printed circuit board. The encapsulated chips will replace both the leadframe and printed circuit board (electrical only) as we now know it in the conventional SIMM module.Type: GrantFiled: September 26, 1995Date of Patent: October 5, 1999Assignee: Micron Technology, Inc.Inventors: Tim J. Corbett, Alan G. Wood