Abstract: A memory array using structure changing memory elements in a reverse biased diode array is disclosed. A memory cell is programmed and read by reverse biasing the diode to overcome the diode's breakdown voltage. The disclosed reversed biased diode array exhibits much less substrate current leakage than a similar forward biased diode array.

Abstract: A rotary drill bit for drilling subsurface formations comprises a bit body having a shank for connection to a drill string, a plurality of primary blades and at least one secondary blade circumferentially spaced and extending outwardly away from a central axis of rotation of the bit, a plurality of cutters mounted along each blade, a majority of the cutters mounted on each of the primary blades having a greater exposure than a majority of the cutters on the secondary blade, and a sweep angle of the secondary blade is less than a sweep angle of the primary blades. The drill bit will exhibit a rate-of-penetration as a function of the size of the cutters on the primary blades, and exhibit a torque profile as a function of the size of the cutters on the at least one secondary blade.

Abstract: A method for fabricating an ultra-small pore or contact for use in chalcogenide memory cells specifically and in semiconductor devices generally in which disposable spacers are utilized to fabricate ultra-small pores or contacts. The pores thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.

Abstract: A variable resistance material-based memory cell is disclosed for use in an electronic memory. The memory cell includes a MOS diode for delivering large amounts of current to the variable resistance material, as needed during programming of the memory cell. In one embodiment, a buried contact under the gate is used as the drain of the device. The buried contact allows formation of a very short channel, causing a "snapback" phenomenon in the MOS diode and thereby greatly increasing the amount of current flow across the device. This buried contact construction has the additional advantage of reducing the area needed for the memory cell. Additionally, the processing is simple and may be performed using the same techniques normally used during the fabrication of electronic memories.

Abstract: A surgical mask for covering a nose and mouth of a person is disclosed. The mask is designed to facilitate the flow of air through the nose. The mask includes a stiff, adhesive strip which, when secured over the nose, opens the nasal passages to allow more air to flow therethrough. In addition, the stiff, adhesive strip prevents exhaled air from escaping through the top of the mask and condensing on the wearer's glasses or other surfaces.

Abstract: The present invention provides a method of fabricating photomasks having a border region and a pattern region, which may be electrically isolated. The border region may include a nontransparent region, such as an opaque chrome layer. The pattern region may include a substantially nontransparent region, such as a leaky chrome layer. The methods of the present invention include placing the photomask in an electrochemical cell and electrically connecting a portion of the photomask to an electrode, and applying a potential, thereby electrochemically transferring a layer between the electrochemical cell and the photomask.

Abstract: A method for chemical vapor deposition onto high aspect ratio features. Process gases including a reactant species are supplied to the surface and sufficient primary energy is supplied to the surface so as to cause the reactant species to deposit on the surface. Additional energy is supplied, preferably in the form of optical energy, that is tuned to be captured by the patterned features so as to slow the deposition rate preferentially on the patterned features.

Abstract: Impurities are added to a conductor layer in a semiconductor process to prevent formation of void spaces and encourage complete filling of contacts. The impurities reduce the melting point and surface tension of a conductor layer, thereby improving filling characteristics during a reflow step. The impurities may be added at any time during the process, including during conductor deposition and/or reflow.

Abstract: A method for fabricating chalcogenide memories in which ultra-small pores are formed in insulative layers using disposable spacers. The chalcogenide memory elements are positioned within the ultra-small pores. The chalcogenide memory elements thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms.