Abstract: An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure having charge stored near both the source and drain. During the erase operation, a negative gate erase voltage is applied along with a positive source and drain voltage to improve the speed of erase operations and performance of the non-volatile memory cell after many program-erase cycles.

Abstract: A Language Controlled Design Flow for the development of integrated circuits (IC) that allows users to Characterize, Synthesize, Simulate, and Analyze IC designs. The Language Controlled Design Flow provides specialized features that enable rapid design development and Intellectual Property (IP) reuse. The language provides the ability to capture a designer's knowledge about the Design Components and Design Processes unique to those components during characterization, synthesis, simulation, and analysis. A feature of this invention is the ability to separate design or design component specific knowledge from the tools used for analysis. This leads to benefits in extensibility, simplicity, accuracy, and performance of the overall tool set. Also provided is a mechanism in which the design process can be fully automated with a Language Controlled Design Flow that can take advantage of the information available in the design, in the design components, and in the design process flow.

Abstract: A clock tree topology distributes a clock signal from a single input terminal 400 to three terminals 421-423 with an equal phase delay. The topology includes four lines 401-404 connected together at a first end 450 with adjacent lines forming right angles. A second end of the line 404 forms the clock signal input terminal 400. A second end of the remaining lines 401-403 are connected to first ends of lines 411-413. Second ends of the lines 411-413 form the terminals 421-423. A right angle is formed between each of the lines 401-403 and the respective one of the lines 411-413 to which it connects.

Abstract: A method, system and article of manufacture is provided to efficiently identify the location of an individual. A first area surrounding the location is obtained by triangulation or other position location methods. A set of street names in the first area is obtained from a database and presented to a user. The user then aids in identifying the present location by selecting the street name or intersection of street names which is closest to his present location.

Abstract: An output buffer includes transistors which tolerate a maximum gate to source, gate to drain, or drain to source voltage (“the maximum tolerable voltage”), such as 2.7 volts, the transistors being configured to produce an output voltage significantly higher than the maximum tolerable voltage. The output buffer includes pull up transistors having source to drain paths connected in series to connect a voltage supply higher than the maximum tolerable voltage to the buffer output. The buffer further includes pull down transistors having source to drain paths connected in series to connect the buffer output to ground. The buffer further includes power supply circuitry to apply gate voltages to the pull up and pull down transistors so that the voltage potential from the source to drain of each of the pull up and pull down transistors is less than the maximum tolerable voltage.

Abstract: An electro-kinetic electro-static air conditioner includes a mechanism to clean the wire-like electrodes in the first electrode array. A length of flexible MYLAR type sheet material projects from the base of the second electrode array towards and beyond the first electrode array. The distal end of each sheet includes a slit that engages a corresponding wire-like electrode. As a user moves the second electrode array up or down within the conditioner housing, friction between slit edges and the wire-like electrode cleans the electrode surface. Another embodiment includes a bead-like member having a through opening or channel, through which the wire-like electrode passes. As the conditioner is turned upside down and rightside up, friction between the opening in the bead-like member and wire-like electrode cleans the electrode surface.

Abstract: An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT's) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications.

Abstract: A method and apparatus for minimizing or eliminating arcing or dielectric breakdown across a wafer during a semiconductor wafer processing step includes controlling the voltage across the wafer so that arcing and/or dielectric breakdown does not occur. Using an electrostatic clamp of the invention and by controlling the specific clamp voltage to within a suitable range of values, the voltage across a wafer is kept below a threshold and thus, arcing and/or dielectric breakdown is reduced or eliminated.

Abstract: Two receive antennas integrated with power detectors are used to align the thrust vector of a vehicle to the boresite of an automotive radar antenna mounted upon the vehicle. In the system, a signal is transmitted from the radar antenna to the Radar Test System (RTS) positioned as an amplitude only interferometer for testing the radar. Signals received by the RTS antennas are provided to amplitude detectors for generation of amplitude plots of a difference signal, or alternative signal, for display. The boresite angle of the radar antenna is then adjusted until the amplitude of the difference signal, or alternative signal, reaches a minimum to align the radar antenna boresite with the vehicle thrust vector. Additional pairs of receive antennas and detectors may be used to provide boresite alignment both in azimuth and elevation.

Abstract: A spine distraction implant alleviates pain associated with spinal stenosis and facet arthropathy by expanding the volume in the spine canal and/or neural foramen. The implant provides a spinal extension stop while allowing freedom of spinal flexion.

Abstract: A spine distraction implant alleviates pain associated with spinal stenosis and facet arthropathy by expanding the volume in the spine canal and/or neural foramen. The implant provides a spinal extension stop while allowing freedom of spinal flexion.

Abstract: A power meter includes components to measure RMS power over an 84 dB range or greater using the I-V square-law relation of a diode for measurements. The power meter includes multiple diodes along with a power distribution manifold which includes power dividers to distribute an input signal to the diodes. In one embodiment, a first power divider (202) distributes power to a first one of the diodes (203), and to the second power divider (204) which distributes power to the second (210) and third (212) diodes. The first power divider (202) is connected without attenuation to the first diode (203). The second power divider (204) is connected to the second diode (210) through a 11 dB attenuator (206), and to the third diode (212) through a 28 dB attenuator (208).

Abstract: A transponder (200) is attached to a laser alignment fixture (210) and used to align an automobile collision avoidance radar antenna boresite with the thrust vector of the vehicle. The alignment fixture (210) has attached reflectors for alignment with two laser beams. To align the collision avoidance radar, the transponder (200) is positioned along the thrust vector of the automobile using a first laser beam (203) aligned perpendicular to a wheel axle. The first laser beam (203) is aligned when transmitted from the wheel axle onto a first piece of reflective material attached to the alignment fixture (210). A second laser (216) is provided parallel to the centerline of the collision avoidance radar antenna to remove azimuth and elevation translation errors between the transponder antenna centerline and the collision avoidance radar antenna centerline. The second laser beam (216) is aligned when transmitted from the automobile onto a second piece of reflective material attached to the alignment fixture (210).

Abstract: A dual paddle end effector robot is disclosed which is capable of parallel processing of workpieces. The end effector includes a lower paddle rotatably coupled to an end of the distal link, and an upper paddle rotatably coupled to the lower paddle. The lower paddle supports a drive assembly capable of rotating the upper paddle with respect to the lower paddle. In one embodiment of the present invention, the dual paddle end effector robot may be used within a wafer sorter to perform parallel processing of workpieces on a pair of aligners within the sorter. In such an embodiment, the robot may first acquire a pair of workpieces from adjacent shelves within the workpiece cassette. After withdrawing from the cassette, the respective paddles on the end effector may fan out and transfer the wafers to the chucks of the respective aligners.

Abstract: A PLD circuit configuration is provided to use less product term lines than a typical PLD to perform an OR operation without using an OR gate. In one embodiment, an inverter is provided between the output of one product term line and the input of an OR gate. The inverter enables the one product term provided to it to provide an OR operation. This is because when two or more elements are ANDed in a product term, inverting the product term creates an OR operation with the elements inverted. With an OR operation provided using a single product term and inverter, less product term lines are needed when performing some operations. In another embodiment, an OR gate output is provided to the first input of a look up table (LUT), while a single product term line is provided to a second input of the LUT. The LUT can be programmably configured to perform a number of Boolean logic functions, such as an OR gate, an XOR gate, etc.

Abstract: A non-volatile memory cell, comprising a semiconductor substrate having a first conductivity type. A control region is formed of said first conductivity type in the substrate and a control region oxide formed over the control region. The cell includes a program element having a first active region of a second conductivity type formed in said substrate, a doped or implanted region adjacent to said first active region, and a gate oxide overlying at least the channel region. An active region oxide covers a portion of the first active region. A floating gate is formed over said semiconductor substrate on said active region oxide and said control region oxide.

Abstract: An ergonomic loading assembly for an I/O port onto which a bare cassette may be easily loaded and unloaded. The loading assembly further provides isolation between the operator and the I/O port after loading of a cassette to minimize safety risks and to minimize the amount of particulates and contaminants around the workpieces while on the port. In a preferred embodiment, the loading assembly includes a cover assembly having a stationary cover section around the port plate, and two pivoting cover sections which open and close like jaws to allow a cassette to positioned within the cover assembly when opened and which enclose the cassette within the cover assembly when closed. The loading assembly further includes a pivoting deck onto which the cassette is loaded when the pivoting cover sections are open. The deck receives the cassette with the workpieces oriented at or near vertical.