Abstract: The e-cell is a computational element for the construction of circuits capable of performing transform invariant pattern recognition, scene segmentation, and regularity extraction in a variety of sensory modes including vision, hearing, olefaction, touch, etc. The e-cell consists of a cell body, an output terminal, and set of tree-connected input regions each of which have one or more input terminals and corresponding stored weights. The e-cell is capable of learning and subsequently discriminating multidimensional (in the mathematical sense) activation patterns applied to its inputs. The strictness with which the e-cell requires the presence in the target of each dimension of a learned pattern is dynamically adjustable, thus making it suitable to recognition of learned patterns under occlusion and various kinds of degradation. The strictness of discrimination across the region dimension is independent of the strictness of recognition within each dimension.

Abstract: A monolithically integrated, multi-layer device is fabricated with single crystal films of desired orientation grown from arrayed nucleation sites on amorphous and/or non-single crystal surfaces. Examples of devices which can be produced are CMOS and bipolar devices in single crystal (100) and (111) Si films on amorphous surfaces such as SiO2 or Si3N4 in processed ULSIC wafers. These devices can be integrated along the 3rd dimension. Thus, 3-dimensional IC's can be fabricated. Similarly, high performance CMOS devices in SiGe films, MESFET, HEMT and optical devices in compound semiconductor films, can be fabricated within processed ULSIC wafers. Further, Si—, GaAs—, and other compound semiconductor-based devices in the respective single crystal films with different orientations deposited selectively in a given level, and in multilevel IC's, can be manufactured.

Abstract: Method and apparatus for etching a silicide stack including etching the silicide layer at a temperature elevated from that used to etch the rest of the layers in order to accomplish anisotropic etch.

Abstract: A resonant microcavity display (20) having microcavity with a substrate (25), a phosphor active region (50) and front and rear reflectors (30 and 60). The front and rear reflectors may be spaced to create either a standing or treaveling eledtromagnetic wave to enhance the efificenty of the light transmission.

Abstract: A decorative plant stand is disclosed with integrated drainage and rotation features. A decorative exterior finish of the stands hides an interior support frame and drainage water collecting and storing subsystems. Wheels or other rotation means are hidden under a base portion of the stand for allowing the stand to be rotated for uniform lighting and ventilation. A shut-off valve is provided within the drainage water collecting subsystem so that the drainage water storing subsystem can be conveniently emptied without spillage.

Abstract: A linear phase detector circuit enables locking of two frequency sources which can operate in the range of 10 GHz with a minimal frequency offset, such as from 0 Hz to 50 KHz. With the frequency sources operating at frequencies F1 and F2 with an offset F2−F1 or F1−F2, the phase detector generates a DC signal indicating a phase offset between a signal F2−F1 or F1−F2 derived from the frequency sources and a reference operating at the desired offset F2−F1 or F1−F2, while eliminating any 2(F2−F1) or 2(F1−F2) component. In this way, the phase detector allows a substantially higher loop bandwidth than the offset F2−F1 or F1−F2, and allows phase tracking independent of the offset. The phase locking circuitry is useful in applications such as providing a variable Doppler shift in a radar signal.

Abstract: A clustered enterprise Java™ distributed processing system is provided. The distributed processing system includes a first and a second computer coupled to a communication medium. The first computer includes a Java™ virtual machine (JVM) and kernel software layer for transferring messages, including a remote Java™ virtual machine (RJVM). The second computer includes a JVM and a kernel software layer having a RJVM. Messages are passed from a RJVM to the JVM in one computer to the JVM and RJVM in the second computer. Messages may be forwarded through an intermediate server or rerouted after a network reconfiguration. Each computer includes a Smart stub having a replica handler, including a load balancing software component and a failover software component. Each computer includes a duplicated service naming tree for storing a pool of Smart stubs at a node. The computers may be programmed in a stateless, stateless factory, or a stateful programming model.

Abstract: An architecture including a speech manager that identifies input, input content, and location of the input (speech, for example), a action scheduler, a dialog manager, and an animation system provides reduced message traffic and streamlined processing for support of animated characters (conversational characters, for example). Speech recognition is provided along with location information to the action scheduler for determination of appropriate expressions for interactive behavior (looking, turn taking, etc.), and speech (or input) content is provided to a dialog manager to determine a substantive response (including speech or other content related responses) and any facial expressions or gestures related to content, but not containing content, are identified, and placed in a communication to the animation system.

Abstract: An intermediate stage for a rail-to-rail input/output CMOS opamp includes a floating current source separating two current mirrors (151-154,155-158), where the ideal current source includes a floating current mirror (500,501,502,503,504,505) enabling an output quiescent current to be provided which does not vary with changes in the voltage rails or the common-mode input voltage, and enabling elimination of input offset caused by the mismatch of the two current sources (164,166). The NMOS transistor (502) has a source-drain path provided in series with a PMOS transistor (505) serving to connect the current mirrors (151-154) and (155-158) and to eliminate input offset.

Abstract: A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions.

Abstract: A spine distraction implant alleviates pain associated with spinal stenosis and facet arthropathy by expanding the volume in the spine canal and/or neural foramen. The implant provides a spinal extension stop while allowing freedom of spinal flexion.

Abstract: A system for computing a path in an electronic map (or other network) starts a pathfinding exploration in the background while the system is waiting for a request to find a path. The system automatically chooses an origin. The system's memory can be divided such that a portion of memory acts as a cache. The data for the nodes in the electronic map are loaded into the cache when needed. The system terminates the pathfinding process when a predetermined condition occurs; for example, a predetermined percentage of the cache is filled. When the system terminates the pathfinding process, the system can start a new pathfinding process from a new origin. Thus, when a user requests a path to be found, the pathfinding process begins with data already loaded in the cache.

Abstract: A device for reducing evaluation time of a matrix representing an electrical circuit. Conductance values of each circuit component in the circuit are written to corresponding models utilizing non-blocking writing techniques. The matrix is represented by a reduced memory structure where each matrix node is represented by a matrix element structure having at least one pointer to a conductance value contained in a model structure corresponding to a circuit component that contributes to a value of the matrix node. A set of rows or columns of the matrix are then processed to calculate final matrix node values independently.