Abstract: A method for implementing a bitmapped graphics system involves creating a logical frame buffer for a program. The method attaches a standardization operation to the logical frame buffer, so that the standardization operation is automatically executed upon the invocation of draw function by an application. The standardization operation serves to perform all of the functions required to properly transmit the contents of the logical frame buffer into the hardware frame buffer, arbitrates access to the logical frame buffer, if necessary, and performs other useful logical operations. In the preferred embodiment, the standardization operation comprises a complementary pre-process and a post-process. The pre-process is invoked prior to the execution of a graphics system draw operation, while the post-process is invoked thereafter. The pre-process and post-process may include more than one distinct pre-function and post-function.

Abstract: A phase compensated switched attenuation device 6 is provided for attenuating high frequency signals while maintaining an insertion loss of less than 1 dB up to 3 GHz. A single GaAs FET 12 is coupled between input port 8 and output port 9 in parallel with a 20 dB pad 10 for switching the device 6 between a through state and an attenuation state. First and second isolation FETs 14 and 16 are coupled between the GaAs FET 12 and pad terminals 18 and 19 to isolate the GaAs FET 12, decrease return loss when the GaAs FET 12 is on, and increase isolation of the GaAs FET 12 from the pad 10 when the GaAs FET 12 is on. A resistor 24 or a series combination of a resistor 24 and capacitor 26 can be coupled to the pad terminals 18 and 19 in parallel with the pad 10 to improve return loss when the GaAs FET 12 is on. Resistors 21, 22, and 23 are also provided to reduce distortion, coupling gates of the FETs 12, 14, and 16 to a plurality of voltage references V1 and V2.

Abstract: An erase-verify operation is performed on a nonvolatile memory cell with an oxide-nitride-oxide structure by using a low drain bias voltage to allow residual charge remaining in the nitride layer after a typical erase operation to be detected effectively with a high degree of sensitivity.

Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.

Abstract: A delay circuit is provided for use in a ring oscillator of a phase locked loop (PLL). The delay circuit includes a differential pair of NMOS transistors 102 and 103 with an NMOS transistor 101 providing the tail current for the differential pair. Complementary NMOS and PMOS load transistors 104,106 and 105, 107 provide loads for the differential transistor 102 and 103. Transistors 111-114 and 121-122 together with an amplifier 130 provide biasing for the delay device. The amplifier 130 has a non-inverting input set to VDD−VCLAMP. As configured, a constant output voltage swing from VDD to VDD−VCLAMP is provided at the outputs VOUT+ and VOUT− of the delay device, independent of a control voltage VCTL used to set the tail current. The NMOS load transistor 104, as opposed to the PMOS transistor 4 in FIG. 1, does not contribute to the gate parasitic capacitance enabling a high operation speed without consumption of more supply current.

Abstract: A spine distraction implant alleviates pain associated with spinal stenosis and facet arthropathy by expanding the volume in the spine canal and/or neural foramen. The implant provides a spinal extension stop while allowing freedom of spinal flexion.

Abstract: A method and computer readable medium for generating a graph which displays amounts of access to computer files, such as URL's on the world wide web, over a period of time. Time is mapped along a central axis, and a plurality of file identifiers is mapped radially about the radial axis as lines having varying distances from the radial axis. The lines may be arranged at angles of rotation about the radial axis and are colored to represent the lexicographical similarity of the nodes. Alpha bending is utilized to reveal lines having an angle of rotations near 0 degrees that would otherwise be concealed by neighboring lines. In an alternative embodiment, a two dimensional graph displays instantaneous access information for a plurality of file identifiers, where angular rotation and color may also be used to represent the grouping of the nodes, and distances of radial lines from an origin represent access values to respective files.

Abstract: A palmtop computer for entering characters using one or more input modes. In one example, a physical sensor is coupled to select the input mode. The physical sensor may be in the form of a button, rocker switch, dial, pressure strip, moveable bar, or accelerometer mounted to the device. The physical sensor may also be mounted to a pen. In another example, a ridge is formed on the digitizer pad and positioned to define input regions associated with particular input mode. In another example, a border is formed around the digitizer pad. The border includes a ridge coupled to select the input mode. The digitizer pad may also be textured. A first textured region is associated with one input mode and a second textured region is associated with another input mode.

Abstract: On a wafer that includes multiple distinct designs in each die region, a memory is included in each die region. The memory stores information specific to the design implemented in the same die region. Such stored information may include a circuit design identifier or a proprietary technology identifier. Such identifiers minimize IC confusion and aid in tracking usage of proprietary technology.

Abstract: Nanocomposite thin films with low dielectric constants are made by the simultaneous deposition of an oxide dielectric and an organic polymer at near room temperatures. Suitable oxides include SiO2, and suitable organic polymers include poly(chloro-para-xylylene). The two dielectric materials, when deposited, form nanocomposites characterized by nanometer-sized domains of dielectric material. The nanocomposite thin films of this invention are useful as dielectric layers for interlevel dielectric (ILD) and intermetal dielectric (IMD) dielectrics in the manufacture of semiconductor devices as well as for thin films for flat panel displays, food wraps, hybrid ceramics, glass, hard disk drives, and optical disk drives. Additionally, the invention comprises semiconductor devices and semiconductor chips made incorporating nanocomposites deposited by chemical vapor deposition.

Abstract: A capacitive structure includes two parallel plate capacitors configured for placing between coaxial cables. The first parallel plate capacitor includes an upper conductive plate and a lower conductive plate that are substantially parallel to one another and separated from one another by a first dielectric material. The second parallel plate capacitor includes an upper conductive plate and lower conductive plate that are substantially parallel to one another and separated by a second dielectric material. The lower conductive plate of the first capacitor is engaged against, and thereby connected to, the upper conductive plate of the second capacitor. A conductive clip connects the upper conductive plate of the first capacitor to the lower conductive plate of the second capacitor.