Patents Represented by Attorney Fogg and Associates, LLC
  • Patent number: 6570880
    Abstract: A telecommunications network is provided. The network uses a ring of ring switches to provide a transport mechanism for data packets that is transparent to the data and protocols contained in the data packets. This transport mechanism is simple and low cost to implement. Such networks can carry, for example, control data between a primary site and secondary sites of a cable network to set up and deliver pay per view, video on demand or near video on demand programming. The network can also be used, in other embodiments, to provide remote access to utility meters, to centralize network management of the cable network, and other appropriate monitoring and control functions.
    Type: Grant
    Filed: August 21, 1998
    Date of Patent: May 27, 2003
    Assignee: ADC Telecommunications, Inc.
    Inventor: Michael H. Coden
  • Patent number: 6567274
    Abstract: An embodiment of the present invention provides a faceplate for a circuit board. The faceplate has first and second prongs protruding from a first end of the faceplate respectively at first and second sides of the faceplate. The first and second prongs are adapted to engage a housing to aid in inserting the circuit board into the housing. A tab protrudes from the first end of the faceplate at a front of the faceplate. The tab lies substantially between the first and second prongs. The tab is adapted to engage the housing to aid in extracting the circuit board from the housing.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: May 20, 2003
    Assignee: ADC DSL Systems, Inc.
    Inventors: Robert Tusan, Tahsin Khairi
  • Patent number: 6563050
    Abstract: A cable assembly is provided. The cable assembly includes an interface plate having a raised outer surface and an inner surface. The inner surface is adapted to engage with a housing. The interface plate includes a recess having a channel that is adapted to receive a cable and an opening through the interface plate at one end of the channel to allow the cable to pass through the interface plate. The recess is adapted to receive a sealant that covers the cable once the cable is placed in the channel.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: May 13, 2003
    Assignee: ADC Telecommunications, Inc.
    Inventors: Gary Gustine, Charles G. Ham, Matthew Kusz, Fredrick Daniels, Michael Sawyer
  • Patent number: 6556245
    Abstract: A video camera is disclosed that can be mounted to a firearm or bow for recording game hunting. The camera has a quick release mount system that allows the video camera to slide on to and off of the weapon with ease. The camera has a liquid crystal display so the hunter can monitor what the camera is recording. A liquid crystal display housing member contains the liquid crystal display and acts as a lense cover when the camera is not recording. Moreover, when the liquid crystal display housing member is moved, from covering the lense, the camera start recording automatically. The video camera also has seals that protect the camera's components from weather and other conditions likely to be encountered while game hunting.
    Type: Grant
    Filed: March 8, 1999
    Date of Patent: April 29, 2003
    Inventor: Larry Allan Holmberg
  • Patent number: 6553871
    Abstract: Embodiments of the present invention provide tools for installing and extracting fuses. In one embodiment, the tool has an elongate handle. A guideway spans the length of the handle, and a pair of jaws, adapted to retain the fuse, protrudes from an end of the handle. A rod is disposed within the guideway and is selectively actuatable within the guideway for releasing the fuse from the jaws.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: April 29, 2003
    Assignee: ADC Telecommunications, Inc.
    Inventors: Michael Sawyer, Matthew Kusz, Fredrick Daniels, Christopher Kachurick
  • Patent number: 6555894
    Abstract: In a semiconductor substrate having a top surface and a PN junction between a first region of one conductivity type formed by masked diffusion into a semiconductor from the surface and a second region of opposite conductivity type formed into a first portion of the first region from the surface, the improvement comprises one edge of the first region being spaced from the edge of the second region such that the doping concentration of the first region at the surface intersection of the four corners of the junction between the first and second regions is lower than it is at some other location in the region.
    Type: Grant
    Filed: April 20, 1998
    Date of Patent: April 29, 2003
    Assignee: Intersil Americas Inc.
    Inventor: James D. Beasom
  • Patent number: 6552392
    Abstract: An integrated circuit having a high voltage lateral MOS with reduced ON resistance. In one embodiment, the integrated circuit includes a high voltage lateral MOS with an island formed in a substrate, a source, a gate and a first and second drain extension. The island is doped with a low density first conductivity type. The source and drain contact are both doped with a high density second conductivity type. The first drain extension is of the second conductivity type and extends laterally from under the gate past the drain contact. The second drain extension is of the second conductivity type and extends laterally from under the gate toward the source. A portion of the second drain extension overlaps the first drain extension under the gate to form a region of increased doping of the second conductivity type.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: April 22, 2003
    Assignee: Intersil Americas Inc.
    Inventor: James D. Beasom
  • Patent number: 6551897
    Abstract: A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: April 22, 2003
    Assignee: Intersil Americas Inc.
    Inventors: Patrick Anthony Begley, Donald Frank Hemmenway, George Bajor, Anthony Lee Rivoli, Jeanne Marie McNamara, Michael Sean Carmody, Dustin Alexander Woodbury
  • Patent number: 6549087
    Abstract: Avariable equalizer is described. The variable equalizer provides for independent control of a number of breakpoints in the frequency response of the equalizer so as to allow the equalizer to be readily tuned to compensate for the tilt of coaxial cables over a wide range of characteristic attenuation. In one embodiment, the variable equalizer includes a two port bridge “T” network with variable top and bottom branches that are independently and selectively adjusted to create a desired frequency response. For example, in one embodiment, the top branches include a number of variable RC networks and the bottom branches include a number of variable LR networks. In some embodiments, PEN diodes provide the variable resistance in these LR and RC networks.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: April 15, 2003
    Assignee: ADC Telecommunications, Inc.
    Inventors: Peter Sung Tri Hoang, Earl A. Daughtry
  • Patent number: 6544879
    Abstract: Methods for manufacturing microchips are provided. A plurality of alternating metallic wiring-layers and non-metallic layers, terminating with a metallic wiring-layer, are formed on a wafer. A plurality of vias is formed for electrically interconnecting various metallic wiring-layers. A plurality of electrically conducting pads is formed adjacent various vias. A passivation layer is formed adjacent the terminal metallic wiring-layer and the plurality of conducting pads. A portion of the passivation layer is removed to expose the plurality of conducting pads. A layer is formed adjacent the passivation layer and the plurality of exposed conducting pads for protecting the microchip against electromagnetic radiation. A portion of the protective layer is removed to expose the plurality of conducting pads. Each conducting pad is electrically isolated from the protective layer. An electrically conducting bump is formed on each conducting pad.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: April 8, 2003
    Assignee: Bae Systems Information & Electronic Systems Integration Inc.
    Inventors: Tushar T. Shah, Keith K. Sturcken, Steven Wright
  • Patent number: 6539546
    Abstract: A telecommunications network is provided. The network uses a ring of ring switches to provide a transport mechanism for data packets that is transparent to the data and protocols contained in the data packets. This transport mechanism is simple and low cost to implement. Such networks can carry, for example, video signals between a primary site and secondary sites of a cable network to provide video on demand, near video on demand, distance learning and other video based services. Such networks can also provide telephony service as voice over IP.
    Type: Grant
    Filed: August 21, 1998
    Date of Patent: March 25, 2003
    Assignee: ADC Telecommunications, Inc.
    Inventor: Michael H. Coden
  • Patent number: 6534347
    Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: March 18, 2003
    Assignee: Intersil Corporation
    Inventors: Jun Zeng, Gary Mark Dolry, Praveen MurAleedharan
  • Patent number: 6535715
    Abstract: A communication system is described. The communication system includes a distribution network between a head end terminal and at least one remote unit. The head end terminal receives upstream telephony and control data modulated on a plurality of orthogonal carriers in a frequency bandwidth over the distribution network. The head end terminal includes a polyphase filter that filters at least the upstream telephony data to provide ingress protection for the modulated orthogonal carriers. The communication further includes a service unit multicarrier modem associated with the at least one remote unit and operatively connected to the distribution network for modulating at least upstream telephony information on at least one carrier orthogonal at the head end terminal to at least one other carrier in the frequency bandwidth.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: March 18, 2003
    Assignee: ADC Telecommunications, Inc.
    Inventors: Mark J. Dapper, Michael J. Geile
  • Patent number: 6526995
    Abstract: A method for removing a slurry from a silicon wafer after chemical-polishing whereby the wafer is subjected to at least 2 or more chemical megasonic baths for a short duration of time. The pH of the first megasonic bath matches the pH of the slurry to be removed.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: March 4, 2003
    Assignee: Intersil Americas Inc.
    Inventor: Diana L. Hackenberg
  • Patent number: 6522166
    Abstract: An electronic system is provided. The electronic system includes a logic device and at least one input/output interface coupled to the logic device. The electronic system further includes an input/output (I/O) device with memory coupled to the at least one input/output interface, wherein the memory of the I/O device is mapped as an address space region that is directly readable and writable by a processor.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: February 18, 2003
    Assignee: ADC Telecommunications Israel Ltd.
    Inventors: Mark Libov, Stan Sacharen, Mark Kaplun, Noam Ben-Moyal
  • Patent number: 6519156
    Abstract: A heat sink is provided that has a leg and a member coupled substantially perpendicular to the leg at a first end of the leg. The leg is surface mountable to a first surface of a printed circuit board at a second end of the leg to receive heat from an electronic device on a second surface of the printed circuit board by a thermally conductive via through the printed circuit board.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: February 11, 2003
    Assignee: ADC Telecommunications, Inc.
    Inventor: Christopher J. Scafidi
  • Patent number: 6504256
    Abstract: A microchip having a passivation layer on an electrically active surface; a multitude of electrically conducting protuberances for electrically coupling the active surface to a substrate; a layer on the passivation layer for protecting against electromagnetic radiation; and a layer on an electrically inactive surface of the microchip for protecting against electromagnetic radiation.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: January 7, 2003
    Assignee: Bae Systems Information and Electronic Systems Integration, Inc.
    Inventors: Tushar T. Shah, Keith K. Sturcken, Steven Wright
  • Patent number: 6493319
    Abstract: A system and method for accessing a number of communication lines by one or more testing devices are disclosed. Each of the communications lines is coupled through the system and includes a first termination at a first telecommunications termination site and a second termination at a second telecommunications termination site. The system includes a number of line access devices, each of which is coupled to at least one of the communication lines terminating at the first telecommunications termination site and at least one of the communication lines terminating at the second telecommunications termination site. One or more monitoring busses are defined by a number of relays, one or more of which is coupled to one of the line access devices. A test device interface, which is selectively coupled to the bus, provides bi-directional connectivity between the selected communication line and a selected testing device coupled thereto.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: December 10, 2002
    Assignee: ADC Telecommunications, Inc.
    Inventors: Marian Kramarczyk, David Foni, Haim Jacobson, Dobrin Tzotzkov
  • Patent number: 6490277
    Abstract: A system and method provide for accessing a plurality of communication lines. Each of a number of line access devices is coupled to at least one of the communication lines. A patch circuit, associated with each line access device, provides for manually establishing a cross-connection between a first and second communication line. A bus couples the first communication line with the patch circuit. A locking circuit is coupled to the bus and the patch circuit. The locking circuit selectively enables and disables patch circuit access to the first communication line in response to a control signal. The line access devices may each comprise a single line card or a front and rear line card pair. A redundant power supply arrangement provides for keep-alive backup power for the front line card in response to a failure of primary supply power delivery to the front line card.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: December 3, 2002
    Assignee: ADC Telecommunications, Inc.
    Inventor: Dobrin Tzotzkov