Abstract: Apparatus and Methods for the self-alignment of separated regions in a lateral MOSFET of an integrate circuit. In one embodiment, a method comprising, forming a relatively thin dielectric layer on a surface of a substrate. Forming a first region of relatively thick material having a predetermined lateral length on the surface of the substrate adjacent the relatively thin dielectric layer. Implanting dopants to form a top gate using a first edge of the first region as a mask to define a first edge of the top gate. Implanting dopants to form a drain contact using a second edge of the first region as a mask to define a first edge of the drain contact, wherein the distance between the top gate and drain contact is defined by the lateral length of the first region.

Abstract: A method for tuning a cavity filter is provided. The cavity filter includes a plurality of tuning members. The method includes selecting a stored set of positional values for the tuning members, driving the tuning members of the cavity filter to the stored set of positional values, and further adjusting the position of the tuning members as necessary to achieve a desired frequency response for the cavity filter.

Abstract: The present invention relates to inductors with improved inductance and quality factor. In one embodiment, a magnetic thin film inductor is disclosed. In this embodiment, magnetic thin film inductor includes a plurality of elongated conducting regions and magnetic material. The plurality of elongated conducting regions are positioned parallel with each other and at a predetermined spaced distance apart from each other. The magnetic material encases the plurality of conducting regions, wherein when currents are applied to the conductors, current paths in each of the conductors cause the currents to generally flow in the same direction thereby enhancing mutual inductance.

Abstract: A circuit card that includes a single ground plane connectable to a chassis-ground and a logic device having a ground pin connected to the single ground plane. The connection between the ground pin and the single ground plane provides a direct path between the logic device and the chassis-ground. A power supply is connected to an input pin of the logic device for providing a logic voltage to the logic device. The power supply is connectable to a battery.

Abstract: A method capable of determining whether a target detected by a radar is a stationary on-road object or not is disclosed, wherein a fluctuation in the reception level of a reflected wave from a target is obtained in relation to the distance of the target, a difference in reception level between a maximum point and a minimum point is obtained from the fluctuation of the reception level, and when the obtained difference is larger than a predetermined threshold value, it is determined that the target is a stationary on-road object. Further, slope over the distance between the maximum point and the minimum point is obtained, and when the obtained slope is greater than a predetermined threshold value, it is determined that the target is a stationary on-road object. Further, the distance between maximum points or between minimum points is obtained, and when the obtained distance is smaller than a predetermined threshold value, it is determined that the target is a stationary on-road object.

Abstract: A transmitter that performs stimulated Brillouin scattering suppression is provided. The transmitter includes a non-linear device having an optical input adapted to receive an optical signal, an amplitude modulation input adapted to receive an amplitude modulation signal, a phase modulation input and an output. The transmitter also includes a stimulated Brillouin scattering (SBS) oscillator/driver having first and second oscillators coupled to the phase modulation input of the non-linear device and an amplifier coupled to the output of the non-linear device. The transmitter further includes a laser coupled to the optical input of the non-linear device.

Abstract: A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor.

Abstract: A integrated access device in a communication network. The integrated access device in one embodiment includes a network port, a plurality of telephony ports, a data port and communication circuit. The network port is adapted to provide dynamic time division multiplex (TDM) interface to a communication network. The plurality of telephony ports are adapted to provide telephony service to subscriber premises equipment. The data port is adapted to provide digital subscriber line (DSL) service to subscriber premises equipment. The communication circuit is coupled to the network port, the plurality of telephony ports and the data port. Moreover, the communication circuit is adapted to carry voice and data signals between the network port and the plurality of telephony ports and the data port. In addition, the integrated access device is line powered over the network port.

Abstract: A junction field effect transistor (JFET), acting as a switch, is coupled between the source and gate of a metal oxide semiconductor field effect transistor (MOSFET). A capacitor is connected in parallel with the MOSFET's “Miller capacitance” by being coupled between the gate and drain of the MOSFET in series with a current limiting resistor. When the JFET is on, it has a low impedance with zero gate voltage and forces the gate to source voltage of the MOSFET to remain near zero and, thus, the MOSFET in a high impedance state, until the capacitor charges to the supply voltage.

Abstract: An FM-CW radar system comprises a modulating signal generating means for changing a modulating signal to be applied to a FM-CW wave, a calculating means for calculating a distance or relative velocity with respect to a target object by performing processing for detection by fast-Fourier transforming a beat signal occurring between a transmitted signal and a received signal, and a control means for determining a detection range based on the calculated distance, and for performing control to change the modulating signal, wherein the modulating signal is changed by changing one parameter selected from among a modulation frequency, a triangular wave frequency, and a transmit wave center frequency. The detection range is set to a distance obtained by adding a prescribed distance to the shortest distance detected, or to a distance obtained by subtracting a prescribed distance from the distance of a fixed object.

Abstract: A low temperature coefficient resistor (TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor.

Abstract: Movement timing stimulators that aid in the relief of the symptoms of neurological movement disorders are provided. In one embodiment, a movement stimulator has a control unit. A stimulator is coupled to an output of the control unit. The stimulator is adapted to provide stimulation to an area of the body of a living subject. A sensor is also coupled to the control unit and is adapted to be disposed external to the body. The sensor is adapted to respond to a physical stimulus and to provide input to the control unit. The stimulator adapts to this physical stimulus to selectively provide at least one of a dual-polarity signal for providing cutaneous stimulation, a phased signal for providing surround sound aural stimulation, and a signal for providing visual stimulation transmitted to the stimulator by the control unit.

Abstract: A central office line unit (COLU) for a pulse code modulation (PCM) upstream and downstream system in a universal digital loop carrier (UDLC) includes a hybrid circuit for transmitting/receiving an analog signal to/from a switch. An analog-to-digital converter is provided for receiving the analog signal from the hybrid circuit and converting the analog signal to a converted digital signal. A digital transmission circuit transmits/receives a digital signal to/from a remote terminal. A quantizer is provided for evaluating and processing the converted digital signal so that only valid states of the converted digital signal are transmitted to the digital transmission circuit for transmission to the remote terminal. A receiver is used for receiving the digital signal from the digital transmission circuit and for evaluating and processing the digital signal so that only valid states of the digital signal are outputted from the receiver.

Abstract: An electronic module having a chassis and a single backplane disposed within the chassis. A plurality of bridge circuit cards is disposed within the chassis and is electrically connected to the single backplane. Each of the plurality of bridge circuit cards is for converting between a local area network protocol and a wide area network protocol. A hub circuit card is disposed within the chassis and is electrically connected to the single backplane so that the hub circuit card is electrically connected to each of the plurality of bridge circuit cards. The single backplane is connectable to each of a plurality of remote units for respectively electrically connecting each of the plurality of remote units to each of the plurality of bridge circuit cards. The single backplane is connectable to a data network for electrically connecting the data network to the hub circuit card.

Abstract: An electronics enclosure is provided. The enclosure includes a modular card cage adapted to receive one or more electronic circuit cards and a heat sink adapted to protrude through an opening of an enclosure and couple to the modular card cage. The modular card cage and the heat sink provide an isolated heat transfer path for heat, produced by each of the one or more electronic circuit cards, to be removed from the enclosure.

Abstract: A reverse path signaling circuit is described which provides less noise and interruption when injecting signals upstream to a head end. The reverse path signaling circuit includes a low pass filter, a status monitor, and a common emitter amplifier. The common emitter amplifier has a emitter region which couples to the status monitor. The status monitor couples to the common emitter amplifier as a single-ended input to the to the emitter region. The status monitor injects status monitor signals into the emitter region for passing the status monitor signals upstream to a head end. The low pass filter is coupled to another input on the common emitter amplifier. An output from the common emitter amplifier is taken at a collector region. The reverse path signaling circuit of the present invention does not require the use of a directional coupler as part of the circuit. Systems and methods are further included within the scope of the present invention.

Abstract: A method of determining electrical parameters of inductive elements includes a novel technique of inverting an impedance matrix representative of said inductive circuit element. The method reduces model simulation time by a factor of 3000. In one embodiment, simulation time of a device model was reduced from 1 hour to less than 3 seconds. The method is suitable for use with circuit element modeling tools, circuit simulation environments, and antenna modeling systems. The method may be applied to inductors, transformers, antennas, etc.

Abstract: A driver circuit for use on an integrated circuit tester. In one embodiment, the driver circuit has a timing circuit and a driver. The timing circuit has two or more inputs to receive data signals at a first frequency and at least one output. The timing circuit generates a control signal having a second higher frequency and outputs signals based on the data signals and the control signal such that the output signals are independent of the effects of timing skew and timing jitter of the data signals. The driver has at least one input coupled to the at least one output of the timing circuit to receive the output signals and couple the output signals to a device under test.

Abstract: An integrated circuit having a MOS structure with reduced parasitic bipolar transistor action. In one embodiment, a MOS integrated circuit device comprises a substrate having a working surface, at least one body region and for each body region a source and a layer of narrow band gap material. Each body region is formed in the substrate proximate the working surface of the substrate. Each layer of narrow band gap material is positioned in a portion of its associated body region and proximate the working surface of the substrate. Each layer of narrow band gap material has a band gap that is narrower than the band gap of the substrate in which each of the body regions are formed. Each source region is formed in an associated body region. At least a portion of each source region is also formed in an associated layer of narrow band gap material.

Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.