Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. In one embodiment, the synchronous memory device comprises an array of memory cells arranged in rows and columns. A clock connection is provided to receive an externally provided clock signal. The memory does not require a precharge time period during a time period between the first and second externally provided active commands.

Abstract: A memory device can read data stored in memory cells using a differential voltage sensing technique. The memory includes a differential voltage sensing circuit having two input nodes. The nodes of the sensing circuit are pre-charged prior to reading the memory cell. The nodes are pre-charged by charge sharing multiple bit lines. In one embodiment, local bit lines having a first charge are coupled to global bit lines having a second charge to provide a desired pre-charge level. The local and global bit lines can have equal capacitance values. The voltages of the bit lines prior to charge sharing can be any selected value, but in one embodiment the local bit lines are discharged to ground and the global bit lines are charged to Vcc. The memory includes a programmable fuse circuit to selectively activate pass circuitry and couple one or more local bit lines to a global bit line in response to the pass command code. This allows the pre-charge level of the sensing nodes to be adjusted after fabrication.

Abstract: A memory device has multiple selectable read data paths. Some of the read data paths include compression circuitry to compress data and decrease test time by testing multiple memories in parallel and/or multiple array banks from the same memory in parallel. A non-compression read path is provided to by-pass the compression circuitry. During memory read operations, therefore, data can be coupled to output buffers without being subjected to delays through a compression circuit. A first compression path can be selected to couple 16 bits from 1 memory array bank to 4 output connections. A second compression path can be selected to couple 64 bits from 4 memory array banks to 4 output connections.

Abstract: A memory device provides a more efficient address decoding operation. In one embodiment, the memory device is a synchronous flash memory that has an array of memory cells arranged in rows and columns. An external device, such as a processor, provides row and column addresses for accessing the memory array. The memory device can include the internal address counter, such as a burst counter. The address processing circuitry includes address input buffers having a first latch circuit coupled thereto, and a multiplexer coupled to receive either the input address signals or addresses generated by the internal address counter. Second latch circuits are coupled to the multiplexer circuits. The second latch circuits, in one embodiment, latch the externally provided address signals coincident with the first latch circuit.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. In one embodiment, the present invention can include a memory device comprising an array of memory cells arranged in addressable blocks and an n-bit status register. The memory includes a control circuit coupled to the n-bit status register to program a first bit of the n-bits to a first state indicating if a program operation is being performed on the array. The control circuit further programs second and third bits of the n-bits to identify one of the addressable blocks while the array is being programmed. A method of operating a memory device includes initiating a write operation on a first programmable location of the memory device using a first processor, and reading a status from status data stored in the memory device during the write operation. The status indicates an identification of the first programmable location.

Abstract: Negative switch circuits are arranged to have a first electrical path coupled between an input and an output of the negative switch circuit and a second electrical path in parallel with the first electrical path for selectively isolating a load from a negative potential node. The first electrical path presents an open circuit in response to a first state of a first control signal and presents a closed circuit in response to a second state of the first control signal. The second electrical path presents an open circuit in response to either a first state of a second control signal or a condition of the load indicative of a defect associated with the load, and presents a closed circuit in response to a second state of the second control signal in combination with a condition of the load not indicative of such a defect. Such negative switch circuits are adaptable to isolate defective portions of a memory device from a negative charge pump during block erase operations.

Abstract: Memory devices having architectures permitting the application of a voltage differential across alternate bitlines facilitate identifying and locating shorts within the memory device with particular reference to flash memory devices. The memory devices include a first plurality of selective coupling devices coupled between a first plurality of bitlines and a first variable potential node. The memory devices further include a second plurality of selective coupling devices coupled between a second plurality of bitlines and a second variable potential node. The first plurality of selective coupling devices are responsive to a first control signal to selectively provide electrical communication between the first plurality of bitlines and the first variable potential node. The second plurality of selective coupling devices are responsive to a second control signal to selectively provide electrical communication between the second plurality of bitlines and the second variable potential node.

Abstract: An automatic gain control circuit for an analog to digital converter is provided. The automatic gain control circuit includes an input, coupled to an output of the analog to digital converter, to receive samples output by the analog to digital converter. The automatic gain control circuit also includes a digital to analog converter that is coupled to selectively adjust a magnitude of an input signal for the analog to digital converter. The automatic gain control circuit also includes a microcontroller. The microcontroller is coupled to the input and the digital to analog converter. The microcontroller is programmed to generate a feedback signal for the digital to analog converter to control the amplitude of the input to the analog to digital converter.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory includes a clock connection to receive an external clock signal, a chip select (CS#) connection to receive a chip select signal, a row address strobe (RAS#) connection to receive a row address strobe, a column address strobe (CAS#) connection to receive a column address strobe and a write enable (WE#) connection to receive a write enable signal. Control circuitry is provided to perform a burst read operation of memory cells in a first block of the memory and interrupt the burst read operation when the chip select signal is active, the row address strobe is either inactive or active, the column address strobe is de-active, the write enable signal is active, and the address signals identify the first block simultaneously during the burst read operation.

Abstract: Clock generator circuits containing a delay circuit having at least one delay element and at least one bypass are arranged to activate the bypass in response to a first logic level presented at the input of the delay circuit and to deactivate the bypass in response to a second logic level presented at the input of the delay circuit. Such clock generators are useful in synchronous memory devices for generating internal clock signals of fixed pulse width from an external clock signal. The internal clock signal is generated from a triggering event, such as a rising edge of the external clock signal, and has a pulse width determined by the delay time of the delay element. The first logic level is generated in response to the beginning of an output pulse of the clock generator while the second logic level is generated in response to the completion of an output pulse of the clock generator.

Abstract: A testing apparatus that comprises an electrical device. A first circuit is in electrical communication with the electrical device. The first circuit including an amplifier. First and second couplers are electrically connected to the first circuit and arranged in series with the amplifier. The amplifier is positioned between the first and second couplers. A second circuit has a first end in electrical communication with the first coupler and a second end in electrical communication with the second coupler. The total gain of the first coupler, the second coupler, the portion of the first circuit between the first and second couplers, and the second circuit is approximately zero.

Abstract: A motorcycle uses a unique suspension system to reduce front end dive during braking. Anti-dive characteristics through full suspension travel provides a smoother ride by reducing the compression damping used in the suspension. The suspension system incorporates a rigid fork, a compression fork and a rocker arm. The front wheel is mounted to the rocker arm such that an axis of the wheel is located along the rocker arm between the rigid fork and the compression fork. A brake is coupled to the axis of the front wheel with a first support member and is connected to the rigid fork with a second support member. A brake linkage which includes a portion of the rigid fork, the rocker arm, and the first and second support members forms an irregular quadrilateral during vertical movement of the front wheel, such that a centerline of the second support member and a centerline of the rocker arm intersect behind the front wheel axis.

Abstract: A system and method for conducting heat from electrical devices mounted on a circuit board is disclosed. A heat sink for conducting the heat is provided that includes a pair of substantially parallel vertical legs and a horizontal member coupled between the pair of substantially parallel vertical legs to form a “U” shape. The horizontal member includes an outer surface and an inner surface both having a layer of thermal interface material. The heat sink is surface mountable to a heat sink mounting pad on a surface of a printed circuit board. The heat sink mounting pad is adjacent to and thermally coupled to a heat transfer pad of an electronic device. The heat sink is thermally coupled to the electronic device.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can detect a brown-out of a supply voltage. The memory device comprises a voltage detection circuit to monitor a supply voltage and provide a signal if the supply voltage drops below a predetermined value. A latch is coupled to the voltage detection circuit and can be programmed to indicate if the supply voltage dropped below the predetermined value. An external controller can read a status of the latch. The memory, therefore, can provide an indication to an external controller that a reset, or initialization, operation is needed.

Abstract: A resonator filter comprising a housing formed with a conductive material. The housing defines a first cavity, a second cavity, and an intermediate wall positioned between the first and second cavities. The housing defines an opening between the first and second cavities. First and second center conductors are positioned within the first and second cavities, respectively. A coupling wire is connected between the first center conductor and the housing. The coupling wire and the center conductor have substantially equal thermal expansion coefficients.

Abstract: A therapeutic hand exerciser includes a resilient core and a fabric exterior lining. The core is soft, pliable and smooth when squeezed. The soft smooth feel of a segmented polyurethane fabric, such as LYCRA®, also provides a more pleasurable feel than a rubber cover. The addition of the thermo plastic urethane (TPU) lining prevents the core material from passing through the fabric cover.

Abstract: A compact gripping device includes a spring that can be retracted to retract ends of the spring via application of a force. The force can be either a downward (push) or upward (pull) force. The spring ends are retracted by removing the force. The spring engages a compact disc either by gripping an inside surface of a hole provided in the compact disc, or by contacting a bottom surface of the compact disc. An embodiment which grips the inside surface of the compact disc allows the compact disc to be axially rotated by the gripper, while the gripper which grips the bottom surface of the compact disc allows for multiple discs to be gripped at one time.

Abstract: A local area network (LAN) type group of data comprising a reserved value, a source media access control (MAC) address, and a destination MAC address. The source MAC address corresponds to a network element that originates the LAN type group of data. The destination MAC address uniquely corresponds to one or more network elements designated to receive the LAN type group of data.