Patents Represented by Attorney Francis A. Varallo
  • Patent number: 4387298
    Abstract: An electronic recognition circuit is described for use in bar code reader systems having postal and commercial applications. Such systems may be required to read codes which are of relatively poor print quality. The present circuit utilizes statistical auto-correlation techniques to reject extraneous ink dots and minor print voids commonly associated with such printing. Additionally, the circuit is skew tolerant and both position and velocity independent of the bar code being processed.
    Type: Grant
    Filed: November 27, 1981
    Date of Patent: June 7, 1983
    Assignee: Burroughs Corporation
    Inventors: David J. Petersen, Paul E. Tartar, Robert S. Bradshaw
  • Patent number: 4381130
    Abstract: The present disclosure describes a connector or socket having particular application for LSI/VLSI integrated circuit (IC) packages with cylindrical interface pins. The connector is characterized by the ease with which the IC package may be inserted therein or withdrawn therefrom, despite the large number of pins involved. In achieving this result, the connector utilizes a unique contact design wherein two opposing cantilever type spring members include respective contoured fingers for capturing and firmly holding an IC package pin during normal circuit operation. The connector also incorporates one or more contact release plates, each having a plurality of cam-like apertures operatively positioned with respect to the connector contacts. Actuation of a release plate moves each pair of contact spring members toward each other, thereby opening the area enclosed by the fingers and providing substantially zero force package insertion or withdrawal conditions.
    Type: Grant
    Filed: September 29, 1980
    Date of Patent: April 26, 1983
    Assignee: Burroughs Corporation
    Inventor: George J. Sprenkle
  • Patent number: 4362991
    Abstract: The present disclosure describes a probe assembly for use in the testing of integrated circuits. More specifically, the probe assembly finds particular application in high density printed circuit board configurations of flat pack integrated circuit (IC) packages. The invention is characterized by its ability to be readily positioned in either coordinate axis, so as to access all of the IC packages regardless of their mounting position. The probe itself is designed to separate and insulate the IC package leads from one another. Moreover, the point of electrical contact of the probe on the leads is predetermined and reproducible. Finally, the probe automatically locks on to the desired IC leads and exerts a force thereon which is independent of that applied by the operator. Electrical and mechanical damage which might otherwise result to the printed circuit board and the IC package is virtually eliminated by the probe assembly.
    Type: Grant
    Filed: December 12, 1980
    Date of Patent: December 7, 1982
    Assignee: Burroughs Corporation
    Inventor: Joseph C. Carbine
  • Patent number: 4307293
    Abstract: An optical reader system configured as a kit for retrofitting the input consoles of existing letter sorting machines of the type used by the U.S. Postal Service. Such machines require that an operator, stationed at a console, enter sorting information for each mail piece, by way of a manually actuated keyboard. The present invention expands the processing capabilities of the machines by permitting the machine reading of mail pieces that have had their address information pre-coded in machine readable form on their respective faces. At the same time, the automatic function does not impair or modify the usual operator controlled console operation when non-coded mail is being processed.
    Type: Grant
    Filed: August 4, 1980
    Date of Patent: December 22, 1981
    Assignee: Burroughs Corporation
    Inventors: Sebastian J. Lazzarotti, Paul E. Tartar
  • Patent number: 4306191
    Abstract: An electronic circuit is described for accurately and rapidly initializing long-time constant amplifiers and the like. More specifically, the circuit is designed to establish quiescent conditions in minimal time and with minimal settling in amplifiers or integrators with internal or external voltage offsets. In performing its initializing function, the circuit utilizes a relatively low resistance network which mirrors the resistive network of the amplifier device and provides a charging path for the integrating capacitor. At the same time, the output of the device is permitted to immediately attain its steady-state voltage amplitude. The present auxiliary network automatically compensates for input offset error, so that quiescent conditions may be established extremely rapidly. Finally, the initialization configuration taught by the invention is characterized by simplicity and a small increase in the component count.
    Type: Grant
    Filed: December 3, 1979
    Date of Patent: December 15, 1981
    Assignee: Burroughs Corporation
    Inventor: Clifford J. Bader
  • Patent number: 4302804
    Abstract: An electronic circuit is described for providing a low current DC supply at increased voltage with high efficiency and minimal hardware complexity. In performing its function, the circuit preferably utilizes a plurality of CMOS voltage-controlled solid state switches in conjunction with a sequenced clock pulse train to implement a compact capacitive-type multiplier. Thus, capacitors are charged in a predetermined order and the charges stacked upon one another to ultimately charge an output storage capacitor to a voltage level which is substantially a desired multiple of the supply voltage applied to the circuit. For descriptive purposes, the present inventive techniques are applied herein to the design for an octupler.
    Type: Grant
    Filed: September 4, 1979
    Date of Patent: November 24, 1981
    Assignee: Burroughs Corporation
    Inventor: Clifford J. Bader
  • Patent number: 4301450
    Abstract: An error detecting unambiguous multi-segmented indicia display method and apparatus is disclosed wherein an "OFF" segment is illuminated differently than an "ON" segment of the display to verify that the "OFF" segment is indeed "OFF" and not a malfunctioning "ON" segment. In the preferred embodiment a pulsating voltage is supplied to the "OFF" segments to provide a lower integrated average voltage and therefore a lower brilliance of display. In an alternate embodiment a contiguous "OFF" segment of one color is provided next to each "ON" segment so as to indicate unambiguously that each non-illuminated "ON" segment is in fact indicating "OFF".
    Type: Grant
    Filed: February 4, 1980
    Date of Patent: November 17, 1981
    Assignee: Burroughs Corporation
    Inventor: Gerald D. Smoliar
  • Patent number: 4296456
    Abstract: The present disclosure describes a multi-layered integrated circuit package especially suited for high density circuit applications, such as those involving LSI or ULSI. The package is characterized by short uninterrupted electrical circuit paths between the integrated circuit chip and an interconnection medium. The use of metallized vias or feed-throughs commonly employed in multi-layered packages have been eliminated. Also, heat dissipation is enhanced by the short thermal path between the chip and the outer package surface. Finally, the signal lead configuration permits the area occupied by the package on the interconnection medium to be significantly less than that of present-day packages having approximately the same number of input/output pins or terminals.
    Type: Grant
    Filed: June 2, 1980
    Date of Patent: October 20, 1981
    Assignee: Burroughs Corporation
    Inventor: Gilbert R. Reid
  • Patent number: 4291300
    Abstract: An electronic circuit is described for providing an analog-to-digital conversion system having an output "delta" format in which a pulse is produced for each defined change in the amplitude of the input signal. The circuit is characterized by minimal hardware complexity and low current drain. In performing its conversion function, the circuit advantageously employs a single capacitor for coupling the input signal into the system as well as for storing precisely controlled voltage increments for effecting the equality of the input signal and a reference potential. The AC coupling afforded by this configuration eliminates the problems attendant with the digitization of a small AC signal superimposed on a large DC component. Additionally, the circuit of the present invention lends itself to the multiplexing of input signals.
    Type: Grant
    Filed: November 1, 1979
    Date of Patent: September 22, 1981
    Assignee: Burroughs Corporation
    Inventor: Clifford J. Bader
  • Patent number: 4287666
    Abstract: The present disclosure describes a side-loading wire wrapping assembly comprised of a specially configured bit and sleeve, for use on semi-automatic wiring machines. Such machines are used to make solderless wrapped connections on terminals emanating from a common plane. The wire wrapping assembly in present use on many of such machines consists of a fixed sleeve substantially enclosing a spring-loaded bit. The arrangement necessitates front-loading of the bit by the operator--a procedure which is tedious and time consuming. The present invention obviates these difficulties by converting the fixed-sleeve assembly from front-loading to side-loading. This is accomplished by providing in the sleeve, a wire feed aperture in contiguity with a longitudinal slot and of orienting the former with a widened portion of the slit formed in the bit periphery by the wire receiving bore.
    Type: Grant
    Filed: December 19, 1979
    Date of Patent: September 8, 1981
    Assignee: Burroughs Corporation
    Inventor: George J. Sprenkle
  • Patent number: 4251905
    Abstract: A device is described for facilitating the application of an identifying label to a specific location on the surface of an integrated circuit package. In performing its function, the device permits an operator to lift a self-adhering label containing the desired indicia from its backing card while visually aligning it in the device. The operator then places one end of the integrated circuit package into the device, thereby effectively aligning the label with a desired location on the package surface so that it may be transferred thereto. The device finds particular application in an actual operative high density packaging system wherein the adjacent surfaces of a pair of integrated circuit packages are visible only through a narrow slot in a package hold-down member. Labels, such as those placed on generic PROM packages by operators immediately after programming, are thus precisely located so that their type designation can be seen through the aforementioned slot.
    Type: Grant
    Filed: August 2, 1979
    Date of Patent: February 24, 1981
    Assignee: Burroughs Corporation
    Inventor: Samuel R. Romania
  • Patent number: 4244672
    Abstract: A system is provided for arranging articles in a predetermined sequence. In mail handling applications, the documents destined for local distribution may be segregated as to the respective routes of the postmen and arranged in sequence within each route in accordance with the mail-stops or street addresses. In such a system, the documents are transported by individual mechanical carriers. Temporary high density storage of the documents is provided by a recirculation buffer subsystem. Based upon system priorities, selected carriers may be taken out of buffer storage, independently of the other carriers. The selected carriers are then circulated in a short transit-time loop from which they exit to one or more output racks, where they appear in sequential order.
    Type: Grant
    Filed: June 4, 1979
    Date of Patent: January 13, 1981
    Assignee: Burroughs Corporation
    Inventor: George E. Lund
  • Patent number: 4243890
    Abstract: The present disclosure describes an isolator/switching assembly for use in a message terminal system. The assembly permits a pair of electronic data processors, one on-line and the other a back-up unit, each processing confidential or so called "red" data, to interface with each other and both units to interface with and control a common peripheral device or I/O port. At the same time, the assembly provides physical and electrical isolation between the processor and the peripheral device and insures the TEMPEST security of the entire system.
    Type: Grant
    Filed: August 23, 1976
    Date of Patent: January 6, 1981
    Inventors: Bruce J. Miller, Gus C. Gadonas, Frank C. Donofrio
  • Patent number: 4236303
    Abstract: The present disclosure describes an unwrap assembly for use on automatic wiring machines. Such machines are employed to make solderless wire-wrapped connections on posts or terminals emanating from the common plane surface of logic cards and the like. For various reasons, such as logic changes or faulty workmanship, the complete or partial removal of the wires wrapped by such machines may be required. The unwrap assembly of the present invention, comprised of a specially designed unwrap tool slidably disposed within a wire coil stripper sleeve and readily mounted between brackets on the wiring machine, performs the removal function in an economical, time-saving and efficient manner.
    Type: Grant
    Filed: July 2, 1979
    Date of Patent: December 2, 1980
    Assignee: Burroughs Corporation
    Inventor: George J. Sprenkle
  • Patent number: 4216350
    Abstract: In accordance with the present invention, there is provided a non-fusible web for supporting a plurality of individual solder rings in a predetermined pattern homologous with that of a plurality of solder tails or terminals on which the rings are disposed during a soldering operation. The invention finds particular application in vapor phase condensation soldering. Use of the non-fusible web provides for the simultaneous placement of a large number of individual solder rings, while eliminating the erratic and often detrimental flow characteristics occurring during the instantaneous fusion of patterned chains or strings of solder rings during a condensation soldering operation.
    Type: Grant
    Filed: November 1, 1978
    Date of Patent: August 5, 1980
    Assignee: Burroughs Corporation
    Inventor: Gilbert R. Reid
  • Patent number: 4195400
    Abstract: The present disclosure describes an improved side-loading wrap tool or wire wrapping bit for use on semiautomatic wiring machines. The latter are employed to make solderless wrapped connections on terminals emanating from a common plane. In contrast to the wire wrapping bits presently used on the aforementioned machines, the wrapping bit of the present invention retains the wire to be wrapped in a section of the bit which is completely separated from the terminal-receiving aperture thereof. Additionally, the configuration of the wire holding section provides a positive insulation stop and ensures the entrapment of the insulated portion of the wire within the bit in preparation for the wrap cycle.
    Type: Grant
    Filed: December 18, 1978
    Date of Patent: April 1, 1980
    Assignee: Burroughs Corporation
    Inventor: George J. Sprenkle
  • Patent number: 4195770
    Abstract: The present disclosure describes electronic circuits for detecting functional failures of random access memory (RAM) devices. The circuits generate a bit pattern sequence for each memory address location and write the pattern into the memory. Subsequently, the pattern is regenerated and compared for equality with the pattern read from the memory. A complete RAM test comprises a sequence of patterns where each pattern is made to fill the entire memory matrix once. The number of test sequence patterns is a function of the bit organization of the RAM under test. Assuming that the device under test is a RAM of the type included within the tester's repertoire of testable memory devices, failure to achieve equality of the write/read patterns is indicative of a defective RAM.
    Type: Grant
    Filed: October 24, 1978
    Date of Patent: April 1, 1980
    Assignee: Burroughs Corporation
    Inventors: Michael K. Benton, Suresh H. Sangani
  • Patent number: 4189201
    Abstract: A latch assembly is described for applying a high clamping force to an electronic component installed in a suitable connector. The latch assembly insures reliable electrical connection between the component circuit leads and the connector contact elements, as well as a good ground connection between the component and a cooling frame which also serves as the system ground. The present invention finds particular application in the clamping of an interconnect cable assembly. The latter includes flat or ribbon-type cables installed in a suitable housing and adapted to be mounted in a connector. The latch is universal in that it is effective with a single full cable assembly, a pair of split assemblies or a single split assembly. Moreover the latch may be easily applied and removed without the use of tools, thereby facilitating system operations which frequently involve the removal, substitution or interchange of cable assemblies.
    Type: Grant
    Filed: March 2, 1979
    Date of Patent: February 19, 1980
    Assignee: Burroughs Corporation
    Inventor: Samuel R. Romania
  • Patent number: 4175728
    Abstract: The present disclosure describes an improved clamp for use with belted cables in the assembly of electronic equipment. In performing its clamping function, the device is adapted to engage the chassis structure upon which the cables are to be routed and terminated. The clamp design is characterized by its effectiveness with a single flat cable or a bundle of such cables. An increase in the clamping pressure exerted upon the cables results in a proportional increase in the force with which the clamp engages the chassis. This assures that the clamp will remain firmly in place during the assembly operation. Moreover, during such operation, the clamp may be easily removed to permit the addition of another cable and then reapplied. Finally, when the wiring of the cable bundle has been completed, the clamp may optionally be removed for use at another location or permitted to remain permanently in place.
    Type: Grant
    Filed: February 1, 1979
    Date of Patent: November 27, 1979
    Assignee: Burroughs Corporation
    Inventor: Thomas R. Ferguson
  • Patent number: 4174566
    Abstract: A tool is described for the holding and insertion of integrated circuit (IC) packages of the type having a metallic heat sink member fused to the chip-enclosing ceramic body. The heat sink member includes a locator or registration hole. The tool finds particular application in connection with a patented high package density island configuration wherein each IC package is secured by means of the registration hole on a retention post of a connector which is mounted between, and in close proximity to, adjacent parallel sections of the island cooling frame. The IC package heat sink member has at least one integral extension adapted to contact the frame. In performing its holding and insertion function, the tool is capable of engaging the sides of the registration hole. The assembler may then convey the IC package to the connector in which it is to be mounted, and positions the hole above the connector retention post.
    Type: Grant
    Filed: May 30, 1978
    Date of Patent: November 20, 1979
    Assignee: Burroughs Corporation
    Inventor: John G. Smith