Abstract: In one embodiment, each of a plurality of sites may produce surplus power. All or a fraction of the surplus power may be supplied to the power grid according to an agreement between the user of a site and an electric utility. A computer of the utility is in communication with a computer at each of a plurality of sites having a local power source. Terms of power provision that include an amount of power to be provided during a specified time of day is communicated between a site and the utility.

Abstract: A mechanism is provided for oversubscribing branch circuits. An active energy management mechanism determines a cumulative wattage rating using power consumption information for a powered element, the power consumption information is for a primary and a redundant portion of the powered element. The active energy management mechanism determines a power reduction power cap to be used by the powered element in the event of a loss of either a primary or a redundant power source supplied to the powered element using the cumulative wattage rating, a branch circuit rating, and a circuit breaker rating for the powered element. The active energy management mechanism sends the power reduction power cap to the powered element in order that the powered element reduces power to the power reduction power cap in the event of the loss of either the primary power source or the redundant power source supplied to the powered element.

Abstract: A mechanism is provided for converting a set of single-layer design rules into a set of split-layer design rules for double patterning lithography (DPL). The set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure are identified. The set of single-layer design rules comprise a first plurality of minimum distances that are required by a set of first shapes in a single-layer design. Each of the first plurality of minimum distances in the set of single-layer design rules are modified with regard to the minimum lithographic resolution pitch constraints for single exposure, thereby forming the set of split-layer design rules. The set of split-layer design rules comprise a second plurality of minimum distances that are required by a set of second shapes and a set of third shapes in a split-layer design. The set of split-layer design rules are then coded into a design rule checker.

Abstract: Enabling storage area network (SAN) component migration are provided. An end-to-end systems management console, referred to as the hardware migration assistant, is provided to simplify the migration steps for a SAN administrator to replace key SAN components. The hardware migration assistant provides a single interface suitable for stepping the SAN administrator through the reconfiguring task faster and with fewer sources of error than the known distributed manual process. The hardware migration assistant of the illustrative embodiments provides an interface through which a user may specify a type of SAN component that is being replaced and identifies the particular SAN components that are being replaced. The hardware migration assistant provides a knowledge base for guiding the user through the replacement operation and the reconfiguring of the SAN components, including the new SAN components, based on the previous configuration of the replaced components.

Abstract: A mechanism is provided for harmonic mean optical proximity correction (HMOPC). A lithographic simulator in a HMOPC mechanism generates an image of a mask shape based on a target shape on a wafer thereby forming one or more lithographic contours. A cost function evaluator module determines a geometric cost function associated with the one or more lithographic contours. An edge movement module minimizes the geometric cost function thereby forming a minimized geometric cost function. The edge movement module determines a set of edge movements for each slice in a set of slices associated with the one or more lithographic contours using the minimized geometric cost function. The edge movement module moves the edges of the mask shape using the set of edge movements for each slice in the set of slices. The HMOPC mechanism then produces a clean mask shape using the set of edge movements.

Abstract: A profiler of a multithreaded process that determines whether a process is runnable but not running by determining whether a process is both waiting for the processor and also not waiting for other events such as I/O. Counters are maintained for each such process that is runnable but not running. Reports are generated summarizing data relating to any process that may be starved due to lack of processor time. Information obtained by the method and apparatus assists developers in optimizing resources in multithreaded environments.

Abstract: Mechanism are provided for model-based retargeting of photolithographic layouts. An optical proximity correction is performed on a set of target patterns for a predetermined number of iterations until a counter value exceeds a maximum predetermined number of iterations in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes in response to the counter value exceeding the maximum predetermined number of iterations. A normalized image log slope (NILS) extraction is performed on the set of target shapes and use the set of lithographic contours to produce NILS values. The set of target patterns is modified based on the NILS values in response to the NILS values failing to be within a predetermined limit. The steps are repeated until the NILS values are within the predetermined limit.

Abstract: A mechanism is provided for determining an incident of a resource in a computing environment. An event pertaining to the resource is processed by a system automation module. The event is represented as an associated event data having parameters of a target state, a target state prior to the event, a current state, and a current state prior to the event. First, the target state is compared to the target state prior to the event to assure that the target state is steady. Wherein a determination that the event is an incident cannot be made after comparing the target state and the current state, the system automation module compares the current state to the current state prior to the event. Upon determining that the event is an incident, the event data is marked and stored in a repository.

Abstract: Improving system resource utilization in a data processing system is provided. A determination is made as to whether there is at least one ceded virtual processor in a plurality of virtual processors in a shared resource pool. Responsive to existence of the at least one ceded virtual processor, a determination is made as to whether there is at least one dedicated logical partition configured for a hybrid mode. Responsive to identifying at least one hybrid configured dedicated logical partition, a determination is made as to whether the at least one hybrid configured dedicated logical partition requires additional virtual processor cycles. If the at least one hybrid configured dedicated logical partition requiring additional virtual processor cycles, the at least one ceded virtual processor is deallocated from the plurality of virtual processors and allocated to a surrogate resource pool for use by the at least one hybrid configured dedicated logical partition.

Abstract: Reducing coherency problems in a data processing system is provided. Source code that is to be compiled is received and analyzed to identify at least one of a plurality of loops that contain a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by a direct buffer. Responsive to an indication that the memory reference is an access to the global memory that should be handled by the direct buffer, the memory reference is marked for direct buffer transformation. The direct buffer transformation is then applied to the memory reference.

Abstract: A mechanism is provided for performing secure recursive virtualization of a computer system. A portion of memory is allocated by a virtual machine monitor (VMM) or an operating system (OS) to a new domain. An initial program for the new domain is loaded into the portion of memory. Secure recursive virtualization firmware (SVF) in the data processing system is called to request that the new domain be generated. A determination is made as to whether the call is from a privileged domain or a non-privileged domain. Responsive to the request being from a privileged domain, all access to the new domain is removed from any other domain in the data processing system. Responsive to receiving an indication that the new domain has been generated, an execution of the initial program is scheduled.

Abstract: Compiler analysis and runtime coherency checking for reducing coherency problems is provided. Source code is analyzed to identify at least one of a plurality of loops that contains a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by at least one of a software controlled cache or a direct buffer. A determination is made as to whether there is a data dependence between the memory reference and at least one reference from at least one of other direct buffers or other software controlled caches in response to an indication that the memory reference is an access to the global memory that should be handled by either the software controlled cache or the direct buffer. A direct buffer transformation is applied to the memory reference in response to a negative indication of the data dependence.

Abstract: A modular processing module allowing in-situ maintenance is provided. The modular processing module comprises a set of processing module sides. Each processing module side comprises a circuit board, a plurality of connectors, and a plurality of processing nodes. Each processing module side couples to another processing module side using at least one connector in the plurality of connectors such that, when all of the set of processing module sides are coupled together, the modular processing module is formed. The modular processing module comprises an exterior connection to a power source and a communication system and at least one heatsink that couples to at least a portion of the plurality of processing nodes on one of the processing module sides and is designed such that, when a set of heatsinks in the modular processing module are installed, an empty space is left in a center of the modular processing module.

Abstract: A mechanism is provided for efficient communication of producer/consumer buffer status. With the mechanism, devices in a data processing system notify each other of updates to head and tail pointers of a shared buffer region when the devices perform operations on the shared buffer region using signal notification channels of the devices. Thus, when a producer device that produces data to the shared buffer region writes data to the shared buffer region, an update to the head pointer is written to a signal notification channel of a consumer device. When a consumer device reads data from the shared buffer region, the consumer device writes a tail pointer update to a signal notification channel of the producer device. In addition, channels may operate in a blocking mode so that the corresponding device is kept in a low power state until an update is received over the channel.

Abstract: A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system.

Abstract: A mechanism is provided for altering access to a network. A virtual I/O server controller in a virtual I/O server operating system receives an indication that an identified communications adapter requires attention. The virtual I/O server controller issues a set of calls to a set of N_port identification virtualization server adapters coupled to the identified communications adapter. Each of the set of calls indicates to each of the set of N_port identification virtualization server adapters a request to move a set of clients from their assigned port on the identified communications adapter to an available port on a failover communications adapter. The set of N_port identification virtualization server adapters moves the set of clients from the identified communications adapter to the failover communications adapter.

Abstract: A mechanism is provided for rescheduling jobs for execution by a computing system. The computing system receives job related data associated with a plurality of jobs to be executed by the computing system, time constraint data, and maximum time shift values associated with the time constraint data. The computing system determines that a start time for execution of a first job of the plurality of jobs should be rescheduled. The computing system receives workload statistics. The computing system determines based on the workload statistics, a first start time for the first job. The computing system compares the time constraint data with the first start time to determine if the first start time is in conflict with the time constraint data. The computing system stores the first start time.

Abstract: Mechanisms of memory management in a real time runtime environment having a garbage collected memory heap are provided. The runtime environment includes a critical real time thread that is precluded from accessing the garbage collected memory heap. The runtime environment further includes a scoped memory area for the allocation of objects therein for access by the critical real time thread. The mechanisms determine whether the critical real time thread is in a defined state in which a delay associated with garbage collection can be accommodated by the critical thread. The mechanisms further initiate, in response to a determination that the critical real time thread is in the defined state, a process of garbage collection of the scoped memory area.

Abstract: A mechanism is provided for increasing efficiency of tasks by observing the performance of generally equivalent code paths during execution of the task are disclosed. Embodiments involve a computer system with software, or hard-coded logic that includes reflexive code paths. The reflexive code paths may be identified by a software or hardware designer during the design of the computer system. For that particular computer system, however, one of the code paths may offer better performance characteristics so a monitor collects performance data during execution of the reflexive code paths and a code path selector selects the reflexive code with favorable performance characteristics. One embodiment improves the performance of memory allocation by selectively implementing a tunable, linear, memory allocation module in place of a default memory allocation module.

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.