Abstract: An integrated circuit achieves a burst mode standby operation for a switched-mode power supply by driving a switching transistor. One winding of a transformer is connected to inputs of two differently biased rectifier circuits and the sum of the output voltages of these circuits is applied to a control terminal of the integrated circuit.

Abstract: A filter circuit having an amplifier stage, an upstream filter and a downstream bandpass filter. The filter includes, inter alia, a rejection circuit tuned to an intermediate frequency and a series circuit, tuned to an image frequency and formed by a capacitor and a .lambda./4 coaxial stub. The inductance formed by the coaxial stub is shared by the series circuit and the rejection circuit.

Abstract: In known processes for controlling a receiver-side appliance, data concerning the identification signal of a program being received are derived automatically from the identification signal transmitted together with the program. The aim of the invention is to allow a program received after the program currently being received to be programmed in a receiver-side appliance without having to input manually individual essential data of the identification signal. According to the present invention, a first identification signal received when a receiver-side control device is activated and a predetermined number of subsequent, different identification signals are counted together and stored automatically in the data contained in the identification signals concerning the identification signal received when the predetermined number is reached and/or the previously received identification signal and the first identification signal.

Abstract: The disclosure is an analog-to-digital converter of half-flash type providing for the multiplexing of two analog input signals and therefore requiring only one converter module. It includes a coarse comparator block used to determine the most significant bits of the converted signals and also determining the voltage range for two fine comparator blocks that determine the least significant bits of the converted signals, wherein each of the input signals is connected to a fine comparator block and said coarse comparator block compares alternatively the first and second input signals with a reference voltage. The analog-to-digital converter can be advantageously used for processing television signals.

Abstract: A process for reducing the friction between a rotating head drum and a tape-shaped recording medium which surrounds the head drum for recording and/or playing back information. In order to shorten access time to information stored on the tape-shaped recording medium, some recorders have the recording medium mounted in a cassette which remains threaded even during rewinding, and surrounds the head drum in the same way as in the play and search modes. Because the tape remains threaded during rewinding, such recorders, also called full-loading recorders, suffer from increased friction between the rotating head drum and the tape moving in the reverse direction. To reduce friction, the speed of rotation of the head drum is increased by a factor, preferably a factor of 2, during rewinding.

Abstract: The secondary winding is connected, via the series circuit of a capacitor and a second diode, to the charging capacitor which delivers the operating voltage. The centre point of the series circuit is connected to earth via a third diode. This enables energy to be recovered, in that the energy stored in the capacitor is delivered back to the charging capacitor during the inhibiting phase of the switching transistor.

Abstract: A more rapid charging of an integrating capacitor of a PLL is provided when large frequency changes are desired. In one embodiment, the phase locked loop (PLL) circuit sinks or sources current to charge or discharge the integrating capacitor. A threshold voltage proportional to a current through the capacitor turns on an augmenting circuit which sinks or sources more current of the proper polarity to the integrating capacitor from an external source until a PLL lock is achieved. Once the lock is achieved, if a small correction current is required by the PLL, the small correction current is below a threshold required to actuate the augmenting circuit, and the PLL loop behaves in the usual manner as if the augmenting circuit were not present. In another embodiment, the integrating capacitor is reduced in value by switchably connecting a second capacitor in series with the integrating capacitor so that the total reduced capacitance of reduced value can be charged more quickly.

Abstract: The disclosure concerns a so-called "auto-zeroing" comparator of two analog input voltages to be compared, and an analog-to-digital converter using a set of auto-zeroing comparators enabling the number of comparators required for an analog-to-digital conversion to be reduced. The main originality of the invention is that this comparator includes a second stage constituted by an inverter function provided in such a way that only a first transistor is controlled on its gate by the previous stage, a second transistor having its gate and drain short-circuited by a switch during the auto-zeroing phase, and a third transistor used as a capacitor and connected to the gate of said second transistor and also to the supply voltage. The present invention is applicable in particular to all types of CMOS multi-comparison ADCs using at least one "auto-zeroing" comparator.

Abstract: A method and apparatus for setting the parameters of an equalizer. Equalizers are used for equalizing distorted signals. However, optimum equalization is only achieved when the parameters of the equalizer are optimally set. To set the parameters of an equalizer optimally, the output signal of the equalizer is rectified in a full-wave rectifier. The output signal of the latter is integrated in an integrator. The parameters of the equalizer are set by a microprocessor according to an algorithm. In one embodiment, when the integration time is predetermined, the parameters of the equalizer is changed until the level of the integrated signal becomes a maximum. In another embodiment, when the maximum level of the integrated signal is predetermined, the parameters of the equalizer are changed until the integration time becomes a minimum.

Abstract: In a broadcast receiver, a dynamic compression of the signal is switched on or off in dependence on whether such a compression has been carried out at the transmitting end. An identification bit is transmitted for identifying this compression at the transmitter end. The object is to create a broadcast receiver which effects automatic switching-on or switching-off of an amplitude compression but manages without a transmitted identification bit. The received audio signal is applied to a signal analysing circuit which determines the scale factors of the signal and generates switching voltages dependent on the scale factors. The present invention has particular applicability for broadcast receivers in a motor vehicle or with subsequent signal recording.

Abstract: The present invention concerns an improvement to the "jog and shuttle" knobs used on electronic or electrical devices, notably video devices such as video recorders. The control according to the invention includes a knob mounted inside a cavity in the face-plate of the control panel such that the external face of the knob is aligned with said face-plate, and a finger fixed to a ring mounted coaxially with the knob, the finger being mounted such that it moves around the arc of a circle in the cavity.

Abstract: The invention concerns an arrangement including a microprocessor controller, PROM memory, and a digital to analog converter (DAC) arrangement for generating a plurality of control voltages for trimming respective ones of a plurality of varactor controlled tunable filters. The controller couples digital control signals to the respective DACs which generate respective analog control voltages which are applied to the respective tunable filters. A tuning voltage generated by a closed control loop, such as phased locked loop also under the control of the controller, is combined with the output control voltages generated by the respective DAC's in a resistance divider arrangement.

Abstract: Switch mode power supplies produce a brief pulse-like load on the mains and have a high harmonic content. Such a high harmonic load on the mains is undesirable. There are increasingly strict regulations for the level of harmonic loads connected to the mains. The present switch mode power supply includes a series circuit formed by an inductor and a diode connected between a charge capacitor, which is dimensioned to be relatively small, and a pickoff of a primary winding of a transformer of the switch mode power supply. A relatively large energy storage capacitor connected to the primary winding is decoupled from the charge capacitor by a second diode. The series circuit produces an additional charging current, which extends the current which is drawn from the mains during one half cycle of the mains voltage, and reduces the amplitude of the current.

Abstract: The present infra-red remote control transmitter understands external formats, and those with toggle-bits and different carrier frequency ranges, and transmits signals in these data formats to the appropriate devices, with or without a toggle-bit. The remote control receives and transmits infra-red formats and comprises an infra-red receiver with a microprocessor and/or with two carrier frequency oscillators to generate two modulation frequencies, in which case it is provided with two infra-red receivers. An externally formatted data word with toggle-bits is subjected, after being read at least twice, to a comparison inside the microprocessor, from which the presence of toggle-bits, their number, position and the carrier frequency of the data word are found.

Abstract: The present invention relates to a method of enhancing the noise Immunity of a phase-locked loop. The phase-locked loop includes a comparator and apparatus for inhibiting the action of the comparator on the phase-locked loop. According to the method, the inhibition is lifted during a main time window resulting from the intersection of a first time window derived from the input signal of the phase-locked loop, and of a second time window derived from the loop-return signal.

Abstract: In a switch mode power supply which includes a transformer for DC isolation and a switching transistor, a control transistor which controls the switching transistor is switched on by an appropriate control voltage during the isolating phase until the collector voltage of the switching transistor has fallen to a minimum. The control transistor is preferably switched on during the isolating discharge time and the subsequent oscillation phase of the transformer.

Abstract: In order to increase decoding safety of the address frame of a teletext page during the reception of teletext data, and in particular of a page containing higher level supplementary data, without having to apply additional error control steps, the address frame for a teletext row is forecast from the decoded material, and if required, with a corrected address frame of the preceding teletext row. The forecast address frame is compared with the actually received address frame of the succeeding teletext row. If a deviation at two or more information units of a byte are detected during the comparison, and if required during decoding of the received address frame, the forecast address frame is used instead of the received address frame for addressing the data stream of the concerned teletext row.

Abstract: A shield assembly for installation on a portion of a printed circuit board is presented. The shield (16) assembly includes shield mounted on the component mounting side of the printed circuit board and has a plurality of support projections (30) inserted through apertures of the printed circuit board to the conductor side where they are mechanically secured and electrically connected to a reference potential. A first shield cover (22) is mounted to the shield at a peripheral edge distal of the printed circuit board. A second shield cover (34) is disposed at the conductor side of the printed circuit board. The second shield cover (34) is provided with two pluralities of protrusions (32, 42). The first plurality of protrusions (32) extends through apertures in the printed circuit board to engage the body of the shield. The second plurality of protrusions (42) engages respective support projections (30) of the shield.

Abstract: An appearance of a double image around moving objects may be reduced or removed by generating motion compensated 100 Hz fields with the objects in correct positions. When, however, the results of this technique are applied to motion compensated upconversion, objects or parts of the picture which fall outside the range of measurable velocities appear on the upconverted display with a very strong double image, resulting from the display of information in the wrong temporal position generated by uncompensated or `fallback processing`. The subjective strength of the double image may be reduced by low pass filtering in a horizontal direction the components in the new fields of the upconverted signal which cause this double image.

Abstract: In order to achieve a greater degree of security in the decoder for the control frame of teletext pages, the control frame is initially selected and decoded from the data stream by means of a bit by bit comparison with a frame word. Thereby, the following steps are carried out in dependence on the number of coincidences occurring during the bit by bit comparison with the frame word:a) if, during the bit by bit comparison, eight coincidences are detected, the control frame is considered to have been identified and the counter is reset;b) if less than eight coincidences are detected, it is determined whether a particular number ("444") or a multiple of this number ("n 444") has been reached on the basis of the count-state of the clock pulse counter, whereby, in the event that this number has been reached, the control frame is considered to have been identified and the counter is reset.