Patents Represented by Attorney, Agent or Law Firm Frederick J. Telecky, Jr.
  • Patent number: 8334190
    Abstract: A one-step CMP process for polishing three or more layer film stacks on a wafer having a multilayer film stack thereon including a silicon nitride (SiNx) layer on its semiconductor surface, and a silicon oxide layer on the SiNx layer, wherein trench access vias extend through the silicon oxide layer and SiNx layer to trenches formed into the semiconductor surface, and wherein a polysilicon layer fills the trench access vias, fills the trenches, and is on the silicon oxide layer. CMP polishes the multilayer film stack with a slurry including slurry particles including at least one of silica and ceria. The CMP provides a removal rate (RR) for the polysilicon layer > a RR for the silicon oxide layer > a RR for the SiNx layer. The CMP process is continued to remove the polysilicon layer, silicon oxide layer and a portion of the SiNx layer to stop on the SiNx layer. Optical endpointing during CMP can provide a predetermined remaining thickness range for the SiNx layer.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: December 18, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Eugene C. Davis, Binghua Hu, Sopa Chevacharoenkul, Prakash D. Dev
  • Patent number: 8330159
    Abstract: An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: December 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey Lee Large, Henry Litzmann Edwards, Ayman A. Fayed, Patrick Cruise, Kah Mun Low, Neeraj Nayak, Oguz Altun, Chris Barr
  • Patent number: 7813462
    Abstract: A novel method and apparatus for defining process variation in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The method and apparatus provide direct measurement of fabrication process variation in circuits without requiring any additional test equipment by utilizing a time to digital converter (TDC) circuit already present in the chip. The TDC circuit relies on the time delay in an inverter chain to sample a high speed CKV clock using a slow FREF clock. Calculation of inverse time provides a direct correlation for fabrication process variation in each die.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: October 12, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Elida Isabel de Obaldia, Robert B. Staszewski, Dirk Leipold
  • Patent number: 7787563
    Abstract: A transmitter employing a sigma delta modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. A technique is presented to synthesize the controllers within a single-loop sigma delta modulator such that the noise transfer function can be chosen arbitrarily from a family of functions satisfying certain conditions. Using the novel modulator design technique, polar and Cartesian (i.e. quadrature) transmitter structures are supported. A transmitter employing polar transmit modulation is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands. Similarly, a transmitter employing Cartesian transmit modulation is presented that shapes the spectral emissions of a hybrid power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: August 31, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Nir Tal, Sameh S. Rezeq, Robert B. Staszewski, Oren E. Eliezer, Ofer Friedman
  • Patent number: 7787558
    Abstract: A method of synchronizing a receiver with a transmitter. The method includes determining number of bits, j, for adjusting a bit stream, where the bit stream is generated from n tones and is dividable into codewords having a codeword length of N bytes, and the number of bits for adjusting the bit stream is determined based upon n and N. The method includes detecting a loss of synchronization indication. In response to detection of the loss of synchronization indication, the method includes adjusting the bit stream by j bits. The method includes determining whether synchronization has been regained. When synchronization has not been regained, the method includes adjusting the bit stream again by j bits. When synchronization has been regained, the method includes terminating adjustment of the bit stream.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: August 31, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Michael Locke
  • Patent number: 7547596
    Abstract: A method of manufacturing a semiconductor device includes forming transistors including gate electrodes and source/drain regions over a substrate. A protective layer is placed over the source/drain regions and the gate electrodes. A portion of the protective layer is removed to expose a portion of the gate electrodes. The exposed portions of the gate electrodes are amorphized, and remaining portions of the protective layer located over the source/drain regions are removed. A stress memorization layer is formed over the gate electrodes, and the substrate is annealed in the presence of the stress memorization layer to at least reduce an amorphous content of the gate electrodes. The stress memorization layer is removed subsequent to the annealing.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: June 16, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Mark R. Visokay, Shaofeng Yu
  • Patent number: 7534668
    Abstract: The buried oxide region has a layer added which etches selectively with respect to oxide, allowing the contacts to a gate or to a back gate to be created without overetching into the buried oxide region.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: May 19, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Patent number: 7519955
    Abstract: In a JTAG test and debug environment, the signal groups for boundary scans can have several lengths including signal groups that are longer that the shift register out. A storage unit is provided with a plurality of storage location lengths. The boundary scan signal groups are stored in a location having a suitable storage capacity. The command that transfers the boundary scan signal group includes a parameter identifying the relevant location. The scan control unit, upon receiving the command, transfers the entire boundary scan signal group as a result this command even if several transfers through the shift register out are required.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Lee A. Larson, Henry R. Hoar
  • Patent number: 7519387
    Abstract: In order to overcome the limitation of the integrated circuit chip inter-connectability resulting from the physical dimensions of the leads, a radio frequency transmitter and/or a radio frequency receiver are included in the integrated circuit chip. Logic signal groups from one integrated circuit chip can be encoded by the modulation on the radio frequency signal and received and decoded by a second integrated circuit chip. The transmitted signal groups can be transmitted in a series format or in a parallel format. Either amplitude or frequency modulation can be used to impose information on the carrier frequency.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Nara Won
  • Patent number: 7519111
    Abstract: In a configuration testing integrated circuits, the system clock signals are forced to the same frequency as the test clock signals. When the test clock signals and the system clock signals have the same frequency, both clock signals can applied to the integrated circuit through a single terminal, whereby providing a terminal for the exchange of other signals with the integrated circuit. Using the same signals for test and system clocks allows selected components to be eliminated.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 7514304
    Abstract: A MOSFET device (100) in a mono-crystalline semiconductor material (101) of a first conductivity type, which comprises a source and a drain of the opposite conductivity type, each having regions of polycrystalline semiconductor (110, 120) and respective junctions (112a, 122a) in monocrystalline semiconductor. Localized buried insulator regions (113, 123) are below the polycrystalline source and drain regions, and a gate (130) between the source and drain regions is located so that the gate channel (134) is formed in bulk mono-crystalline semiconductor material. As an example, the semiconductor is silicon, the first conductivity type is p-type, and the localized buried insulator is silicon dioxide. The semiconductor material may also include silicon germanium.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Gregory E. Howard
  • Patent number: 7510923
    Abstract: Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: March 31, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Manoj Mehrotra, Karen Hildegard Ralston Kirmse, Shirin Siddiqui
  • Patent number: 7512928
    Abstract: A method of making a mask design having optical proximity correction features is provided. The method can include obtaining a target pattern comprising a plurality of target pattern features corresponding to a plurality of features to be imaged on a substrate. The method can also comprise generating a mask design comprising mask features corresponding to the plurality of features to be imaged on the substrate and controlling the aspect ratio of at least one of the features of the plurality of features to be imaged on the substrate by positioning a sub-resolution assist feature proximate to the corresponding mask feature.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: March 31, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Scott William Jessen, Mark Terry, Robert Soper
  • Patent number: 7508781
    Abstract: A new protocol system and method is described that utilizes a Schedule Information Vector (SIV) protocol for saving power in wireless local area networks. The protocol includes an access point, one or more stations, and an SIV frame including an association ID for identifying one of the stations and a scheduled wake-up time for the identified station. The access point originates and transmits the SIV frame protocol of the scheduled wake-up time to the stations. The SIV frame protocol of the wireless network is further operable to dynamically adjust the scheduled wake-up times of the stations, a sequence of the wake-up times, a periodic wake-up time, a plurality of wake-up times, and a duration of the wake-up times of the stations. These adjustments may be made based on network traffic, traffic buffering times, data priorities, data length, and data rates.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: March 24, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Yonghe Liu, Jin-Meng Ho, Matthew B. Shoemake
  • Patent number: 7509391
    Abstract: A multi-processor system 8 includes multiple processing devices, including DSPs (10), processor units (MPUs) (21), co-processors (30) and DMA channels (31). Some of the devices may include internal MMUs (19, 32) which allows the device (10, 21, 30, 31) to work with a large virtual address space mapped to an external shared memory (20). The MMUs (19, 32) may perform the translation between a virtual address and the physical address associated with the external shared memory (20). Access to the shared memory (20) is controlled using a unified memory management system.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: March 24, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Gerard Chauvel, Serge Lasserre, Dominique Benoit Jacques d'Inverno
  • Patent number: 7508698
    Abstract: Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets during write operations. The write method first rapidly raises the wordline to a lower read voltage level for access, then after a time delay that allows the cells in the selected row to establish a stabilizing differential voltage on the associated bitlines, raises the wordline voltage to a boosted or higher write voltage level. An SRAM bitline enhancement circuit may also be utilized in association with the SRAM memory array and writing method, for enhancing the differential voltage produced by an SRAM memory cell of the array on associated first and second bitlines of the array of conventional SRAM cells (e.g., a conventional 6T differential cell). In one implementation, the SRAM bitline enhancement circuit comprises a half-latch or a sense amplifier connected to associated bitline pairs of the array for amplifying the differential voltage.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: March 24, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Patent number: 7508728
    Abstract: Methods and apparatus to provide refresh when an out of range address is received are disclosed. An example method of providing a refresh signal to a memory cell includes receiving a memory address on address lines ranging from a most significant bit address line to a least significant bit address line. A memory driver logic device is coupled to the memory cell. An out of range logic decoder is coupled to provide a fixed logic input to a first input of the memory driver logic device. Address logic is provided to cause the memory driver logic device to enable the memory cell if the memory address is a local out of range address.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: March 24, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Steve Richard Jahnke, Hiromichi Hamakawa
  • Patent number: 7502247
    Abstract: Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets during write operations. The write method first rapidly raises the wordline to a lower read voltage level for access, then after a time delay that allows the cells in the selected row to establish a stabilizing differential voltage on the associated bitlines, raises the wordline voltage to a boosted or higher write voltage level. An SRAM bitline enhancement circuit may also be utilized in association with the SRAM memory array and writing method, for enhancing the differential voltage produced by an SRAM memory cell of the array on associated first and second bitlines of the array of conventional SRAM cells (e.g., a conventional 6T differential cell). In one implementation, the SRAM bitline enhancement circuit comprises a half-latch or a sense amplifier connected to associated bitline pairs of the array for amplifying the differential voltage.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: March 10, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Patent number: 7499368
    Abstract: A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device not using a delay locked loop (DLL) device to synchronize clock signals. The system further comprises a logic coupled to the first and second DDR memory devices. The logic is adapted to receive data from the first and second DDR memory devices by way of a single conductive pathway.
    Type: Grant
    Filed: February 7, 2005
    Date of Patent: March 3, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Ashwin K. Rao, Sang-Won Song
  • Patent number: 7498639
    Abstract: An integrated BiCMOS semiconductor circuit has active moat areas in silicon. The active moat areas include electrically active components of the semiconductor circuit, which comprise active window structures for base and/or emitter windows. The integrated BiCMOS semiconductor circuit has zones where silicon is left to form dummy moat areas which do not include electrically active components, and has isolation trenches to separate the active moat areas from each other and from the dummy moat areas. The dummy moat areas comprise dummy window structures having geometrical dimensions and shapes similar to those of the active window structures for the base and/or emitter windows.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: March 3, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Philipp Steinmann, Scott Balster, Badih El-Kareh, Thomas Scharnagl, Michael Schmitt