Abstract: An apparatus for presenting a substantially linear capacitive output at at least one output locus in response to a voltage input at an input locus, the voltage input varying over a voltage range, includes a plurality of switching units coupled with the input locus. Each respective switching unit of the plurality of switching units is coupled with one output locus of the at least one output locus. Each respective switching unit presents a contributing capacitive output at the one output locus. The contributing capacitive output exhibits a generally linear response to the voltage input over a segment of the voltage range. All the respective switching units cooperate to establish the substantially linear capacitive output over substantially all of the voltage range.

Abstract: Low voltage transistors are used in high voltage environment. The low voltage transistors may be used in the path of processing of a signal to increase the throughput performance. By using high voltage supply associated with the high voltage environment, a higher SNR may be attained. Various techniques are implemented to ensure that the low voltage transistors are not damaged by prolonged exposure to high voltages.

Abstract: A front end signal processing method and apparatus for processing a signal from an image sensor are provided for readily clamping a black level, improving the manufacturing yield, and reducing the power consumption. A luminance detector/digitizer receives a sensor output signal from an image sensor, detects luminance information included in the sensor output signal, and generates a digital luminance signal representative of the detected luminance information. A digital processor receives the digital luminance signal, and multiplies the digital luminance signal by a predetermined gain code to generate the multiplication result as a front end processed signal output. An optical black clamp receives the digital luminance signal from the luminance signal detector/digitizer and supplies a feedback signal produced from the digital luminance signal to the luminance signal detector/digitizer to clamp a black level of the luminance signal to a constant value.

Abstract: A memory circuit and method for reducing gate oxide stress is disclosed. A first data word is stored at a first address in a nonvolatile memory circuit 604. The first address 820 and the first data word 842 are stored in a volatile memory circuit 602. A first external address 608 is applied to the volatile memory circuit. The first external address is compared to the first address. The first data word is produced from the volatile memory circuit on a data bus 610 when the first external address matches the first address. The first data word is produced from the nonvolatile memory circuit on the data bus when the first external address does not match the first address.

Abstract: A dynamic current generator 30 is disclosed in which a common-mode input range is provided which is asymmetric toward the bottom rail VEE. An embodiment of the invention is also disclosed used in an asymmetrical dynamically biased amplifier system 34.

Abstract: A first data processor (GPP) can manage resources of a second data processor (DSP) by making a remote procedure call (RPC) to the second data processor to invoke on the second data processor a program that supports management of data processing resources of the second data processor. The second data processor executes the program in response to the remote procedure call.

Abstract: A software system is provided that tracks employee and contractor operation/certification of fabrication equipment and processes is provided to ensure that only qualified personnel are allowed to process the materials. The system is real time with an auto-update features, Web enabled, dynamic tool interface with automatic record checking and reporting.

Abstract: A semiconductor integrated circuit comprises contact pads located over active components, which are positioned to minimize the distance for power delivery between a selected pad and one or more corresponding active components, to which the power is to be delivered. This minimum distance further enhances dissipation of thermal energy released by the active components. More specifically, a semiconductor integrated circuit comprises a laterally organized power transistor, an array of power supply contact pads distributed over the transistor, means for providing a distributed, predominantly vertical current flow from the contact pads to the transistor, and means for connecting a power source to each of the contact pads. Positioning the power supply contact pads directly over the active power transistor further saves precious silicon real estate area.

Abstract: Semiconductor devices and fabrication methods are disclosed, in which one or more low silicon-hydrogen SiN barriers are provided to inhibit hydrogen diffusion into ferroelectric capacitors and into transistor gate dielectric interface areas. The barriers may be used as etch stop layers in various levels of the semiconductor device structure above and/or below the level at which the ferroelectric capacitors are formed so as to reduce the hydrogen related degradation of the switched polarization properties of the ferroelectric capacitors and to reduce negative bias temperature instability in the device transistors.

Abstract: A multichannel frequency domain equalizer improves the subchannel signal to noise ratio by canceling correlated noise that is caused by deterministic spreading at the receiver that introduces correlation into the subchannel noise vector.

Abstract: A de-interleaver-de-puncturer architecture is scalable and capable of achieving a higher data throughput than that achievable using a conventional disjointed de-interleaver-de-puncturer architecture. The higher data throughput is achieved without increasing the clock speed of the de-interleaver. The scalable de-interleaver-de-puncturer architecture is also less complex than a conventional disjointed de-interleaver-de-puncturer architecture.

Abstract: Ferroelectric memory cells and fabrication methods are provided in which the memory cell comprises a ferroelectric capacitor in a capacitor layer above a semiconductor body, and a cell transistor with first and second source/drains formed in an active region of the semiconductor body. The active region extends along a first axis in the semiconductor body, and the cell includes a gate electrically coupled with a wordline structure that extends along a second axis, wherein the first axis and the second axis are oblique.

Abstract: Based on monitored quality of various frequency channels between first and second frequency hopping wireless communication devices, communications between the first and second devices can be scheduled with respect to a predetermined frequency hopping pattern such that communications are advantageously transmitted on selected frequencies that are more likely than others to provide acceptable communication performance.

Abstract: A method, system and materials for use in hydrogen gettering in conjunction with microelectronic and microwave components that are generally hermetically sealed in an enclosure typically referred to as a “package”. Gettering materials that can be used include titanium with or without a hydrogen permeable coating or covering, alloys of zirconium-vanadium iron and zeolites and several ways to apply these materials to the package. In addition, the hydrogen permeable material can be used over a vent from the interior of the package to the exterior wherein hydrogen will escape from the package interior when the hydrogen concentration within the package is greater than without the package.

Abstract: An apparatus is provided for configuring data cells received in a telecommunications process in a continuous stream of data cells of fixed length and each comprising a header and a user data part. The apparatus comprises a processing unit, adapted and configured so that it is able to check data cells for the presence of empty cells, discard the data cells consisting of empty cells and then check the user data parts of the data cells less the empty cells—without the need to buffer the same—as to whether they belong together, and then to assemble the user data parts of the data cells belonging together into a frame. The apparatus may be integrated in, a modem and is also particularly suitable for data cells existing as ATM cells for receiving by an ATM system. The invention relates in addition to a correspondingly sequencing method for configuring data cells.

Abstract: A fourth order delta sigma analog-to-digital converter is presented, comprising a passive delta sigma modulator including a passive filter, a quantizer, and a digital-to-analog converter in a first feedback loop, and an active filter having a large gain factor in a second feedback loop around the passive delta-sigma modulator.

Abstract: A semiconductor chip having a planar active surface including an integrated circuit protected by an inorganic overcoat; the circuit has metallization patterns including a plurality of contact pads. Each of these contact pads has an added conductive layer on the circuit metallization. This added layer has a conformal surface adjacent the chip, including peripheral portions of the overcoat, and a planar outer surface; this outer surface is suitable to form metallurgical bonds without melting. The chip contact pads may have a distribution arrayed in the center of the chip in close proximity to the chip neutral line; the distribution may leave an area portion of the active chip surface available for attaching a thermally conductive plate. The chip may further have a non-conductive adhesive layer over the overcoat, filling the spaces between the added conductive layers on each contact pad.

Abstract: A memory circuit and method to improve signal margin is disclosed. The circuit includes a memory array arranged in rows 702, 704, 706 and columns 750, 752 of memory cells. Each row of memory cells is connected to a respective wordline. Each column of memory cells is connected to one of a bitline and a complementary bitline. An active wordline accesses a respective row of memory cells. The memory circuit includes a plurality of precharge circuits 724, 726, 728. Each precharge circuit is connected to a respective column of memory cells and coupled to receive a precharge signal PRE. An active precharge signal renders a respective precharge circuit conductive. A control and decode circuit 700 changes an inactive wordline signal to an active wordline signal while the precharge signal is active.

Abstract: A technique is provided to linearize a MOS switch on-resistance and the nonlinear junction capacitance. The technique linearizes the sampling switch by using a buffer having substantially unity gain with proper DC shift to drive an isolated bulk terminal of the MOS well to improve the spurious free dynamic range (SFDR). In this way, the 2nd-order effect such as nonlinear body effect (VT(VSB)) and nonlinear junction capacitance (Cj(VSB)) can be substantially removed.

Abstract: An augmented pseudo-noise sequence (10) is generated from a two or more pseudo-noise sequences, using LFSRs or other such devices. A segment (16) of a one pseudo-noise sequence (14), having an arbitrary length, is inserted into another pseudo-noise sequence (12) at an arbitrary position, making the augmented sequence difficult to decipher by a third party. Additional segments of arbitrary length can also be inserted at arbitrary positions for further complexity.