Abstract: A distinctive estimating method using a concise depiction, organization, and presentation of time, related to the number of items accomplished, to produce a Historical Data Block of information, that is a stable inference base. These Blocks of information can be stored, referenced, anatomized, multiplied or divided and restacked, to create other accurate totals and estimates. This stable Block easily allows the accurate calculation of future duration times and item quantity totals. The calculated item quantities can be used to calculate current item costs and totals, by using a current item cost database. Or the item totals can be printed and sent out, requesting a quote, or sent out as purchase orders. The accurate duration times can be used to automatically produce a schedule, concurrently with the estimate, by using a predefined templet.

Abstract: A data processing system and method for performing a wavelet-like transformation and a corresponding inverse wavelet-like transformation is disclosed. The wavelet-like transformation is performed on input data so as to produce decomposed data. For each set of decomposed data samples of the decomposed data, each decomposed data sample of the set is produced by computing a weighted sum of a predefined set of data samples selected from (A) subsets of the set of input data samples, (B) one or more spatially shifted subsets of the set of input data samples, (C) the sets of decomposed data samples, and (D) one or more spatially shifted sets of the sets of decomposed data samples. The weighted sum is computed using only add and bit shift operations. Similarly, the inverse wavelet-like transformation is performed on decomposed data so as to produce reconstructed data.

Abstract: An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between each other, and that cooperate so as to perform circuit verification tasks than would be very difficult to perform using only the HDL circuit simulator. The circuit simulation verifier is coupled to the HDL circuit simulator so as to control the HDL circuit simulator's operation, including specifying conditions under which the HDL circuit simulator is to stop simulation of a specified circuit and specifying input signal waveforms to be used by the HDL circuit simulator. The circuit simulation verifier receives signal waveforms generated by the HDL circuit simulator for specified watched signals. The circuit simulation verifier then determines whether predefined logical combinations of the watched signals meet specified operational correctness and/or performance criteria within specified time frames.

Abstract: A chemical dispensing system controller is used in conjunction with a mechanism for dispensing specified chemicals and a device that transmits trigger signals to the control system for requesting chemicals to be dispensed. The controller receives and accumulates sequences of the transmitted trigger signals. Each trigger signal sequence is preceded and followed by a period of time of predefined duration during which no trigger signals are received. At least some of the trigger signals in some of the trigger signal sequences are not received simultaneously. Also, the number of distinct chemical feed requests that can be communicated using the accumulated trigger signals exceeds the number of distinct trigger signals. The controller maps a first subset of the accumulated trigger signal sequences into chemical feed requests, each of which requests a quantity of a corresponding chemical. The controller enables the dispensing of chemicals in accordance with the chemical feed requests.

Abstract: An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers.

Abstract: A computer system has a CPU, a stack cache and a main memory. The main memory is a conventional untagged memory, where each memory location is a word having a bit size that is an integer power of 2 (e.g., 32, 64 or 128 bits per word). However, at least one stack cache associated with the CPU (and preferably integrated with the CPU on the same semiconductor circuit or in the same chip set) is a tagged memory where each data word of the stack cache has an associated tag. Whenever the stack cache overflows with data, at least a portion of the contents of the stack cache are stored in a previously established location in main memory so as to make room for storing additional data in the stack cache. In this stack cache swap out operation, the data values and tags in N evaluation stack entries of the evaluation stack cache are copied to the previously established main memory location.

Abstract: A data processor supports the use of multiple memory models by computer programs. At a device external to a data processor, such as a memory controller, memory transactions requests are received from the data processor. Each memory transaction request has associated therewith a memory model selected from a predefined plurality of memory models. In a preferred embodiment, the predefined memory models supported are SSO (strong sequential order), TSO (total store order), PSO (partial store order) and RMO (relaxed memory order). Data representing pending memory transactions are stored in one or more pending transaction buffers and a pending transaction status array. The pending transaction status data includes memory transaction order data that indicates which of the pending memory transactions can be performed before other ones of the pending memory transactions.

Abstract: A data and clock recovery circuit includes a front end circuit for receiving a data signal encoded with a Manchester or other bi-phase level code having a sequence of bit frames, and for outputting a recovered data signal and a recovered clock signal in accordance with transitions in the data signal that overlap with a window signal. A window generation circuit generates the window signal in accordance with a delay control signal, and includes circuitry that delays and transforms the recovered clock signal into the window signal. A delay control circuit generates and adjusts the delay control signal. A phase comparison circuit compares the recovered clock signal with leading and lagging portions of the window signal, and generates signals that adjust the delay control signal when the recovered clock signal overlaps with either of the leading and lagging portions of the signal.

Abstract: A data encoder and method utilizes a node list for storing a list of nodes in the data array to be processed, a branch list for storing a list of tree branches in the data array to be processed and a set list for storing a list of data sets. The method begins by initially storing in the node list node identifiers representing a predefined set of nodes in the data array, corresponding to coefficients generated by a last iteration of a data decomposition procedure. Also, it initially stores in the branch list branch identifiers representing tree branches corresponding to a predefined subset of the nodes initially listed in the node list. Each such tree branch has an associated root node and a branch depth value indicating how many node layers intervene between the root node and the nodes of the tree branch closest to the root node. The set list is initially empty, and a parameter called the LayerLimit value is also initialized.

Abstract: A method for reducing stray conductive material near vertical surfaces in semiconductor manufacturing processes comprising the following steps. Deposit the gate oxide, polysilicon and cap oxide layers. Apply a Poly1A mask. The Poly1A mask pattern comprises the Poly1 areas that are part of the final circuit layout as well as additional Poly1 areas that are included to provide planar surfaces to prevent stringer formation. Etch the cap, polysilicon and gate oxide layers to partially form the transistor gate structures. Form oxide spacers on the sides of the transistor gate structures. Apply a source/drain mask. Deposit source/drain dopants to form diffusions. Deposit an interlayer dielectric. Mask and pattern contacts to the diffusions and the Poly1 layer. Deposit blanket TiN/Ti layer(s). Pattern the TiN/Ti layer(s) using a TiN/Ti mask and a dry anisotropic etch. Patterning the TiN/Ti layer(s) may create TiN/Ti stringers along vertical surfaces of the interconnect layer.

Abstract: An audio signal analyzer and encoder is based on a model that considers audio signals to be composed of deterministic or sinusoidal components, transient components representing the onset of notes or other events in an audio signal, and stochastic components. Deterministic components are represented as a series of overlapping sinusoidal waveforms. To generate the deterministic components, the input signal is divided into a set of frequency bands by a multi-complementary filter bank. The frequency band signals are oversampled so as to suppress cross-band aliasing energy in each band. Each frequency band is analyzed and encoded as a set of spectral components using a windowing time frame whose length is inversely proportional to the frequency range in that band. Low frequency bands are encoded using longer time frames than higher frequency bands.

Abstract: In a cluster of computer nodes, each node has network interface and at least one processor. Transmission of a multipart message from a first node to a second node is initiated by sending to a network interface of the first node a sequence of PIO store and DMA store commands, each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node, the sequence of the PIO store and DMA store commands corresponding to a predefined message component order. The first node's network interface packetizes the sequence of PIO and DMA commands to generate an ordered stream of data transfer packets whose order corresponds to the predefined message component order, and transmits the ordered stream of data transfer packets to the second node so as to store the respective components of the multipart message in their respective specified memory locations in the second node in the predefined message component order.

Abstract: When a client computer requests data from a disk or similar device at a server computer, the client exports the memory associated with an allocated read buffer by generating and storing one or more incoming MMU (IMMU) entries that map the read buffer to an assigned global address range. The remote data read request, along with the assigned global address range is communicated to the server node. At the server, the request is serviced by performing a memory import operation, in which one or more outgoing MMU (OMMU) entries are generated and stored for mapping the global address range specified in the read request to a corresponding range of local physical addresses. The mapped local physical addresses in the server are not locations in the server's memory. The server then performs a DMA operation for directly transferring the data specified in the request message from the disk to the mapped local physical addresses.

Abstract: A method and system are disclosed for measuring a temperature of a body in a non-contact mode based on heat flux measurement. The system includes a temperature measurement apparatus to be positioned in close proximity to a body for measuring the temperature of the body. The temperature measurement apparatus comprises a thermally conducting element, a first and a second temperature sensor, and a temperature modulation arrangement. The first and second temperature sensors are mounted in the conducting element and each measures a temperature of the conducting element. The temperature modulation arrangement modulates the temperature of the conducting element until the temperatures at the first and the second temperature sensors are substantially the same. When these temperatures are equalized, heat flux into the conducting element is zero and the temperature of the conducting element represents the temperature of the body. The apparatus thus enables accurate non-contact temperature measurement of a body.

Abstract: The present invention pertains to a system and method for predicting the protein fold of a target amino acid residue sequence of unknown protein structure. A target sequence is represented by a sequence of residue variability types that utilizes positional variability information present in an associated family of homologous sequences to the target sequence. The use of the positional variability information increases the likelihood of matching the target sequence with a known protein structure. In a first preferred embodiment, a target sequence is mapped into a sequence of residue variability types that are based on the solubility variability present between amino acid residues in homologous sequences. In a second preferred embodiment, each residue variability type represents a cluster of residue types at each position of aligned sets of homologous protein sequences. Each distinct cluster represents a pattern of residue variability at various positions in sets of homologous protein sequences.

Abstract: A clock and data recovery circuit has an input port for receiving a data signal representing a sequence of data values, a pulse generator, a clock generator and a data storage element. The pulse generator generates a pulse whenever a data value change is detected in the received data signal. The clock generator generates a clock signal having an associated frequency and phase. The clock generator receives each pulse produced by the pulse generator so as to synchronize the clock signal's phase with data value changes on the input port. The data storage element stores data values in the data signal at times dictated by the generated clock signal. The data values stored by the data storage element is the recovered data signal and the generated clock signal is the recovered clock signal.

Abstract: The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e.

Abstract: A computer system includes a data processor, a primary translation lookaside buffer for storing page table entries and translating virtual addresses into physical addresses, local memory coupled to the data processor for storing data and computer programs at specified physical addresses, and remotely located memory coupled to the data processor by a computer network for storing data at specified remote physical addresses. The computer system further includes a remote translation lookaside buffer (RTLB) that stores a plurality of remote page table entries. Each remote page table entry represents a mapping between a range of physical addresses and a corresponding range of remote physical addresses. The primary translation lookaside buffer translates a virtual address asserted by the data processor into a physical address.

Abstract: A distributed computer network comprising of unconfigured network home client computers, and at least one autoconfiguration server. The network may also include sales servers and local service provider servers. The home network client computer determines on power on time if it possesses the requisite configuration information. If the requisite configuration information is lacking, the home network client computer sends a configuration request along with client computer identifying information to the autoconfiguration server. On receiving the configuration request from a home network client computer, the autoconfiguration server uses the client identifying information to determine the local service provider information and client computer specific data. The autoconfiguration server determines the local service provider information by looking up a directory of local service providers, the directory being stored on the autoconfiguration server or on some local service provider server.

Abstract: A route planning mechanism receives a target set denoting a set of available targets, a set of target parameter thresholds for binning target parameters, a set of mission objectives and a corresponding set of mission thresholds for binning the mission parameters. The route planning mechanism may also receive an avoidance set denoting obstacles to be avoided. The mission objectives define a number of distinct target parameter priority orderings, each associated with a respective mission status. Successive best next targets are selected and added to a selected target sequence list until a mission completion criteria is satisfied. Each best next target is selected by determining a mission status in accordance with the previously selected targets, and a corresponding target parameter priority ordering.