Abstract: A high speed analog-to-digital conversion method and apparatus including a plurality of parallel analog-to-digital converters is disclosed. A clock signal is applied to each of the analog-to-digital converters at different phase relation to increase the equivalent sampling frequency by multiplexing the outputs into a serial form. A reference signal such as a linear ramp or sawtooth signal is used to maintain the correct phase relation, thereby eliminating any errors due to differences in electrical characteristics among the analog-to-digital converters. Such correction may be performed automatically by using a CPU before digitizing an analog input signal or at any desired time.

Abstract: Disclosed herein is a circuit for protecting an inhibitable tristate data driver from damage due to an over current. A logic comparator circuit compares input and output logic levels of the data driver, and inhibits the driver causing the output to go to a tristate if a fault occurs.

Abstract: A linear wideband differential amplifier includes a variable gain stage comprising two cross-coupled differential amplifiers and differential current source to compensate for thermal distortion, to minimize transient response distortion, and to eliminate signal attenuation at the center gain setting.

Abstract: A supply voltage driver for one or more monolithic differential amplifiers sharing common power supplies comprises an additional monolithic differential amplifier operated as a voltage follower suspended between a current source and a current sink. Reference Zener diodes are coupled between the voltage follower output and the power supply terminals of the differential amplifiers to establish operating voltages which track an input signal. Additional current-boosting transistors are provided to provide fast slew rate during signal transitions. Overdrive circuitry is provided to limit the maximum and minimum signal levels.

Abstract: A logarithmic converter circuit comprising an emitter-coupled pair of transistors and a pair of operational amplifiers is provided with a temperature-stabilized environment so that accurate logarithmic conversion is facilitated. One of the pair of transistors is utilized as a temperature sensor to provide a temperature control voltage, which in turn controls the power applied to a heating element disposed adjacent the pair of transistors to maintain a constant semiconductor junction temperature. The heating element may suitably be one or more transistors disposed proximate the pair of transistors on a common substrate. The absolute temperature of the sensor transistor base-to-emitter junction is established by the use of precise gain-setting components, and by adjusting the temperature reference voltage for the correct system gain.

Abstract: The cascode feed forward amplifier is modified to correct alpha-induced error. A pair of resistors are serially disposed between the bases of a pair of common-base amplifiers to generate an error voltage proportional to the input signal. The error voltage is applied to the correction amplifier to provide an appropriate correction current.

Abstract: A diagnostic extender test apparatus for use with a processor-based product under test incorporates analog and digital measurement functions and logic stimulus functions to give a complete diagnostic picture of the product under test. The diagnostic extender test apparatus according to the preferred embodiment has its own microprocessor system and may be operated as a stand-alone instrument as well as an extension of a product under test.

Abstract: A time interval meter for measuring extremely short time intervals includes a timing circuit operable at a fast predetermined rate over the time interval between first and second events, and operable at a slow predetermined rate which is precisely scaled to the first rate over a time interval between the occurrence of the second event and the upper limit of a predetermined timing window. During the slow ramp period, clock pulses are counted to provide a count which is proportional to that portion of the predetermined timing window occupied by the slow ramp interval. The fast ramp time interval may then be readily attained by subtracting the slow ramp interval from the total time of the timing window. The circuit includes a control circuit, a timing circuit including a capacitor and a pair of selectable constant current sources, and a counter.

Abstract: An amplifier is connected between the inverting and non-inverting inputs of an inverting feedback amplifier to substantially reduce distortion caused by inherent physical properties of the semiconductor devices.

Abstract: A waveform acquisition circuit for both real-time and equivalent-time acquisition modes with a smooth transition between modes. The circuit includes a control circuit which causes an analog-to-digital converter to take samples of an analog waveform in precise time relationship with preselected data points along the time axis of the waveform. The data points may be preselected in accordance with a variable increment.

Abstract: A variable current source having a programmable current-steering network is provided in which a plurality of field-effect transistors both provide current switching and form an integral part of the current source. This is accomplished by switching the field-effect transistors into and out of the feedback loop of a voltage follower, which in turn is connected to a current-setting resistor. Reference voltage for the current-setting resistor is provided by a variable voltage generator. The field-effect transistors are switched by means of a programmable digitally-switched bias generator circuit.

Abstract: A high-speed acquisition system employing an analog memory matrix is provided in which sample-hold elements connected to an analog bus are arranged in rows and columns to form an M.times.N matrix. The system is operable in a fast in-slow out mode, and the analog memory matrix may be implemented on a single integrated-circuit semiconductor chip.

Abstract: A waveform storage system is provided in which waveform envelopes or maximum signal deviations along a waveform are detected and stored. A sampling clock operates at a predetermined fixed rate independently of a recording clock which is operable at rates determined by the sweep speed and is equal to or slower than the sampling clock. Data from an analog-to-digital converter is simultaneously applied to at least one latch and at least one comparator to be compared with the latch output. If the absolute value of the signal is greater than that stored in the latch, the latch is updated with the new value. The contents of the latch are clocked into memory by the recording clock.

Abstract: An improved common-emitter cascode f.sub.T doubler amplifier is provided with a feed-forward amplifier circuit to compensate for non-linearities and thermal distortion. The feed forward amplifier senses distortion at the emitters of the f.sub.T doubler amplifier transistors and injects a correction current into a pair of output nodes. The amplifier is also provided with a common-base transistor output stage.

Abstract: A time-multiplexed CCD transversal filter includes N filter sections each comprising N substantially identical CCD's connected in parallel. An N-phase clock is connected to each filter section to provide a sampling frequency f.sub.s which is N times the clock frequency f.sub.c. The output taps of all the devices in a filter section are weighted in a predetermined manner and summed, and the outputs of all the filter sections are multiplexed to provide a continuously valid output.

Abstract: A display system for a digital oscilloscope includes an interpolator for interpolating between stored waveform samples and providing additional samples at the interpolated values to thereby increase dot density of the resulting display.

Abstract: A circuit including a peak detector detects the distortion of the leading corner of a square-wave reference signal in the over-compensated condition of an attenuator probe and turns on an indicator light. The light turns off as the probe is adjusted to the properly compensated condition because the distortion is no longer detected.

Abstract: Jitter due to sample uncertainty in a digital oscilloscope is reduced by horizontally shifting each frame of a repetitive waveform display to provide an apparent time coincidence of each frame. The time interval between a fixed point on the successive waveforms and the next succeeding clock edge is measured, and a correction voltage is produced to offset the sweep voltage by the corrected amount.

Abstract: A signal-envelope display system for a digital oscilloscope includes a memory for storing minimum and maximum signal values in adjacent storage locations, an address counter for sequentially addressing the memory, and a control circuit for selecting the least significant bit of the address count signal arriving at the memory from the least significant bit of the address count signal, a fixed logical low, or a fixed logical high to there by select every address location of the memory, or only the even locations, or only the odd locations over a given count cycle. The values retrieved from memory are converted to analog values and a vector generator connects the analog values to provide connected minimum and maximum values, connected maximum values, and connected minimum values for display. A signal-envelope display is provided by superposing the three displays.

Abstract: A digital oscilloscope is provided with a display system which permits intensified time dots to be positionable between samples on a displayed waveform. The display system has a time dot memory having at least twice the number of addressable storage locations as a waveform memory. An address counter drives the time dot memory and the waveform memory, with time dot memory address count including one or more lesser significant bits than the waveform memory address count. The resolution of the time measurement provided by one or more time dots may be increased by increasing the time dot memory space and adjusting the corresponding number of address count bits to clock the memory at the commensurately higher rate.