Abstract: A multiplexed display interference compensation system for minimizing the apparent intensity modulation of an oscilloscope waveform display caused by closely spaced, individually imperceptible interruptions of the waveform required to maintain refreshed readout display is provided. The system includes a charge pump circuit for adding a current pulse to a waveform intensity control signal in response to a control signal from display multiplex control so as to increase the waveform intensity just after the interruption.

Abstract: An apparatus for time aligning data acquired by one test instrument with corresponding data acquired by another test instrument is disclosed. A set of binary codes, representative of a set of instructions executed by a microprocessor disposed within a user's prototype circuit, are acquired by said one test instrument. With the acquisition of each of said binary codes, a count is developed in a counter indicative of each said acquisition. A multitude of binary data is acquired, independently of the acquisition of the set of binary codes, by said another test instrument, the multitude of binary data being representative of the functions performed by a set of components present within said user's prototype circuit. The binary codes acquired by said one test instrument and the binary data acquired by said another test instrument each have associated therewith a count developed from said counter.

Abstract: An improved bipolar analog switch comprising selectable emitter-coupled pairs of bipolar transistors in combination with an emitter follower output bipolar transistor is provided with means for matching operating characteristics of the selected emitter-coupled pair to eliminate thermal distortion and to provide precise signal replication. Also, a simplified TTL-compatible digital switch control circuit is provided.

Abstract: Disclosed herein is a system for addressing a memory pack having a plurality of memory chips such as RAMs or ROMs. Each memory chip receives address signals and a chip enable signal. A chip selector generates the chip enable signal in response to a feedback signal from the memory pack provided in response to the memory address lines. Since each memory pack excludes the chip selector circuitry, the memory packs can be made smaller in size. The memory packs are in effect self-configuring since they control the feedback of the address signals to the chip selector which generates the chip enable signals. Many types and capacities of memory packs can be mixed in the system since the pack determines the memory address space in which it resides.

Abstract: A compensation circuit is described for use in a line scan type recording apparatus where an electron beam is scanned on the face of a fiber optic cathode-ray tube (FOCRT) in synchronization with a movable recharging medium. The compensation circuit includes a charge pump circuit, an integrator circuit, and a current source. The charge pump circuit draws a constant charge from the integrator circuit in response to a repetitive series of stepper pulse corresponding to the velocity changes in the recording medium. The current source generates a constant current that flows into the integrator circuit and is equal to the average DC current flowing out of the integrator circuit via the charge pump circuit. The output voltage of the integrator circuit is used for controlling the vertical displacement of the electron beam of the FOCRT in synchronization with the movable recording medium.

Abstract: A method and apparatus for automatically detecting peak values of an applied unknown electrical signal employ a binary search technique in which a digital signal is converted to analog reference voltage levels one bit at a time from the most significant bit to the least significant bit to be compared with the unknown signal until finally a digital signal is produced which corresponds to a peak value. By selecting and controlling the comparator slope, both positive and negative peaks may be detected. The search for positive and negative peaks of signals occurring in one or more signal channels may be interleaved to decrease total detection time. From the detected values, a triggering voltage level may be arithmetically computed.

Abstract: A method and apparatus for generating two phase locked digital clocks of different word rates particularly suited for a graphic and alphanumeric computer display terminal. Master and slave clock generators are used to generate output pulses at every N-th and M-th clocks of a common clock. A phase lock loop including the master clock generator and a phase lock counter dividing the common clock by the factor of the least common multiple of N and M is used to synchronize the slave clock generator.

Abstract: A charge coupled device (CCD) with separately addressable input signal gates is operated in the potential equilibrium mode. With properly selected voltage potentials the CCD can be used as a high speed linear detector of a variable analog signal without the need of preceeding independent sample and hold or peak detector circuits. The result is the efficient minimum/maximum detection of an analog signal in a fast-in/slow-out digitizer.

Abstract: A novel Schmitt trigger circuit is disclosed in which the hysteresis is increased in response to low amplitude input signals and decreased for high amplitude input signals. The result is a trigger circuit which can automatically optimize trigger detection for an oscilloscope or counter in the presence of noise on the input signal.

Abstract: A microprocessor controlled system is provided which is responsive to displacement information such as rotation rate and position of a rotary knob for controlling instrument functions such as display scrolling, the setting and display of measurement conditions (operating parameters), and the entering and display of alphanumeric data.

Abstract: Disclosed herein is an apparatus for displaying a logic waveform on a raster scan display device such as a CRT. A part of an input logic signal is delayed for forming a former bit, and the input logic signal acts as a present bit. A memory device stores a special pattern determined in accordance with results of logic operation of the present and former bits. An image dot of the pattern is addressed by the present and former bits and raster line position (number) information, and the output therefrom is applied as an intensity control signal to the display device. Since the memory device does not need FONT information, this invention needs very little software manipulation of data, and the capacity of the memory device is small. In addition, this invention can display glitches and graticule tick marks.

Abstract: A method and circuit for quickly adjusting the frequency of a phase lock loop controlled oscillator to match a reference frequency signal by starting the reference frequency signal at essentially zero initial phase coincident with a zero crossing of the oscillator output. The reference frequency signal is provided by dividing a higher source frequency signal a predetermined amount. Upon receipt of an initialization signal the divider and the phase lock loop are inhibited. Upon the occurrance of a zero crossing the divider and loop are enabled so that the reference signal starts at zero phase within a predetermined period following the zero crossing, and the loop thereafter adjusts the oscillator frequency.

Abstract: A state variable oscillator with leveler circuit and with a feedforward circuit for improving the oscillator's rejection of leveler-induced distortion. The feedforward circuit combines a signal representative of a leveler-distorted feedback signal with the main oscillator output to reduce the amount of harmonic distortion, below a certain order, appearing in the output.

Abstract: A digital signal sampling system is disclosed for reconstructing the time relationship of digital data signals sampled by two sampling clock signals with different unrelated timebases. The digital data signals sampled may be the same data signal or two different data signals sampled simultaneously in two separate sampler circuits at two different unrelated sampling clock frequencies or timebases to produce first and second sampled data signals. A timebase correlation circuit produces first and second time correlation signals in the form of binary level signals in response to the receipt by a last clock pulse detector of first and second store clock signals which are derived from first and second sampling clock signals. The time correlation signals indicate by their binary level the source of the last previous clock pulse of the first and second store clock signals which was received by the timebase correlation circuit.

Abstract: Apparatus for displaying a logic timing diagram on a raster scan type display device is disclosed. A logic signal is sampled and representations thereof stored in a RAM. The RAM contents are read repeatedly in synchronism with a raster scan operation, and the read-out signal is delayed by a predetermined time which is shorter than one bit cycle of the read-out signal. Logical gating functions, OR, exclusive-OR and NAND gates, receive the delayed and undelayed signals, and provide output signals from which the display of the "High" level, edges and "Low" level of the logic timing diagram are derived. Since it is not necessary to convert the logic signal to display codes and rewrite a display RAM, high speed scrolling and magnification can be obtained quickly and easily.

Abstract: An oscilloscope vertical calibration system is provided in which gain control elements in one or more vertical input channels are automatically controlled with respect to cursor voltages applied to the vertical output amplifier. Such calibration process is performed for each deflection factor setting either manually or automatically and the correct gain control signals are stored in memory.

Abstract: An oscilloscope is provided with a dual time base system in which the nonlinear startup segment of the main sweep is eliminated before delay time comparison, thereby facilitating accurate differential measurements down to and including the triggering event (zero time). System delays are built in to ensure that the displayed sweep trace also begins at the left edge of the viewing screen, and, moreover, the triggering event may be viewed on both the main and delayed sweeps. The built-in system delays may be programmable to facilitate delay matching of vertical channels or time matching of independent sweep operation.

Abstract: A signal coupling circuit suitable for use in a high-speed signal acquisition probe comprises separate high-frequency and low-frequency signal transmission paths from input to output. The low-frequency path includes a mechanism for variably shifting the DC voltage level at the circuit input to offset quiescent or average voltage levels of an input signal. Values of impedance elements for both the high-frequency and low-frequency transmission paths may be selected to provide predetermined input and output impedances without compromising signal fidelity or limiting signal bandwidth.

Abstract: The present invention provides a system for applying a fixed level D.C. voltage and a square wave signal sequentially to a voltage divider including a resistor of a known impedance and the device under test. The square wave ranges from a value which is substantially equal to the ground level to a level that is substantially twice the nominal value of the fixed D.C. level, thus the average value of the square wave signal is substantially equal to the nominal value of the fixed level D.C. voltage.With each of these signals applied on at a time to the voltage divider, the voltage across the device under test is applied to a voltage detector via a low pass filter. The output of the low pass filter for each applied voltage signal is the average of the voltage signal which appears across the device under test. The value of these average voltages are stored and then compared.

Abstract: A delay compensation method and apparatus for digital display systems includes a differential clock generator which controls the timing of progenitor digital signals in separate signal-processing channels so that reconstructed horizontal and vertical analog signals arrive at a display device in a precise time match. Thus, timing errors may be adjusted out while the signals are still in digital form to provide an undistorted display.