Patents Represented by Attorney Gerald M. Fisher
  • Patent number: 6670265
    Abstract: An integrated circuit wafer and a manufacturing process for etching low K spin-on dielectrics such as HSQ in a High Density Plasma etch reactor utilizes roof and wall temperature to improve across-the-wafer uniformity, and a mixture of C4F8 and C2F6 etch gases to eliminate mid via etch stop and to maintain selectivity over underlying etch-stop layers.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: December 30, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Fei Wang, James K. Kai, Angela T. Hui
  • Patent number: 6633083
    Abstract: A structure and method for determining barrier layer integrity for multi-level copper metallization structures in integrated circuit manufacturing. Novel testing structures prevent any conducting residues of the copper CMP from diffusing into the dielectric layer. Barrier layer integrity is tested by performing CV or IV measurements between the copper lines and the silicon wafer.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: October 14, 2003
    Assignee: Advanced Micro Devices Inc.
    Inventors: Christy Mei-Chu Woo, Young-Chang Joo, Todd Lukanc
  • Patent number: 5977542
    Abstract: An integrated circuit manufacturing process for substantially eliminating negative electrostatic charge on a wafer surface after resist processing, comprising contacting the wafer with a dilute electrolyte solution having positive ions, restores the fidelity of CD's as measured by low-voltage SEM'S.
    Type: Grant
    Filed: September 11, 1997
    Date of Patent: November 2, 1999
    Inventors: Bhanwar Singh, Subash Gupta, Bryan Choo
  • Patent number: 5939763
    Abstract: A process for growing an ultra-thin dielectric layer for use as a MOSFET gate oxide or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density of electron traps, and impedes dopant impurity diffusion from/to the dielectric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: August 17, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ming-Yin Hao, Robert Bertram Ogle, Jr., Derick Wristers
  • Patent number: 5936307
    Abstract: A method for reducing stress in a TiN layer of a metallization structure, and a silicon wafer portion made by this method. The surface of the dielectric under the TiN is roughened using a water polish with a hard pad, to provide micromounts and valleys on the dielectric surface.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: August 10, 1999
    Assignee: Advanced Micro Devices, inc.
    Inventors: Diana M. Schonauer, Subhash Gupta, Paul Besser, Bhanwar Singh
  • Patent number: 5916855
    Abstract: A polishing slurry composition and its method of making for planarization of silicon semiconductor wafers by chemical mechanical polishing of the wafer. A slurry formulation utilizing a ferric salt tungsten oxidizer, an ammonium persulfate titanium oxidizer, a fatty acid suspension agent, alumina particles with a small diameter and tight diameter range, coated with a solubility coating, and a chemical stabilizer, provides high tungsten and titanium polish rates with high selectivity to silicon dioxide, and good oxide defectivity for use in tungsten local interconnect applications. A method for making a tungsten slurry includes first thoroughly blending small diameter alumina particles with a tight diameter range in an aqueous concentrate with a suspension agent, then mixing with water and oxidizers. Ferric salt tungsten slurries made by this method provide excellent tungsten polish characteristics for via plug and local interconnect applications.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: June 29, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven C. Avanzino, Christy Mei-Chu Woo, Diana Marie Schonauer, Peter Austin Burke
  • Patent number: 5825066
    Abstract: An improved manufacturing process and an improved device made by the process for retarding diffusion of implanted dopants during subsequent high-temperature processing. A layer of an electrically inactive species is implanted well below the active dopant layers, and the excess interstitials due to damage from the electrically inactive species layer form a retarding gradient which opposes dopant diffusion. Using this process, shallow source-drain junctions can be achieved, and lateral encroachment of LDD implants under the gate can be minimized.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: October 20, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mathew S. Buynoski
  • Patent number: 5807790
    Abstract: A photolithographic substrate mask patterning method which enables the reduction of changes in critical dimensions which occur in prior art etching of organic photoresist and the underlying organic i-line bottom anti-reflection layer (BARL) on a non-planar substrate. Based on the minor difference in the total carbon and oxygen content between the organic photoresist and the organic BARL, a differential in polarization is achieved using a pure N.sub.2 plasma for ion etching at certain selected conditions and a selectivity is achieved between the etch rate of the organic photoresist as compared to the etch rate of the organic BARL.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: September 15, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Subash Gupta, Christopher F. Lyons
  • Patent number: 5789318
    Abstract: An improved process for forming titanium silicide layers on semiconductor device silicon regions which have native oxide thereon utilizes a reactively sputter deposited layer of TiH.sub.x.ltoreq.2 followed by a rapid thermal anneal in a nitrogen bearing gas. This process results in lowered silicidation activation energy and lower anneal temperature requirements. Production throughput is improved with respect to prior art methods of removing the native oxide or minimizing its negative effect on silicide formation. The same process produces a titanium nitride/titanium silicide bilayer on silicon, and a titanium nitride/titanium bilayer on silicon dioxide. The thickness of the titanium nitride layer over silicon dioxide is enhanced by the use of TiH.sub.x.ltoreq.2 in place of Ti layers used in prior art, thus improving the utility of the titanium nitride as a diffusion barrier layer.
    Type: Grant
    Filed: February 23, 1996
    Date of Patent: August 4, 1998
    Assignee: Varian Associates, Inc.
    Inventors: Michelangelo Delfino, Ronald C. McFarland
  • Patent number: 5789802
    Abstract: An improved process for forming shallow arsenic-doped source/drain regions in MOS devices utilizes a two-step arsenic implant which lowers the surface arsenic concentration while maintaining sharp junction profile and desired junction depth. Minimizing the excess arsenic in the surface region improves silicidation characteristics.
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: August 4, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Nicholas H. Tripsas
  • Patent number: 5789315
    Abstract: An improved integrated circuit manufacturing process for forming interlevel dielectrics in multilevel metallization structures eliminates extrusions of metal into vias following via etch. The deposition temperature of the conformal dielectric liner is controlled relative to the subsequent degas temperature, thereby lowering thermal compressive stresses in the metal layer.
    Type: Grant
    Filed: July 17, 1996
    Date of Patent: August 4, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul R. Besser, Robin W. Cheung
  • Patent number: 5761254
    Abstract: A method and apparatus for generating a data signal from a transmitted data signal that has been distorted by duty cycle jitter. A locally generated symbol signal is propagated in a delay line such that taps along the delay line emit bit phase signals that are used to clock transitions of the data signal. The position of the data transitions are accorded a numerical value with reference to the bit boundaries and numerically averaged to determine a most desired time to detect the logic level of the data sample.
    Type: Grant
    Filed: January 31, 1996
    Date of Patent: June 2, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Michael N. Behrin
  • Patent number: 5670707
    Abstract: A chromatography system and method employing an empirical method for determining the ratio ##EQU1## for a chromatography column with improved accuracy by establishing experimental conditions for at least one of the parameters of temperature, pressure and flow and measuring the other parameters and calculating the ratio ##EQU2## using the Poiseville equation for a chromatography column.
    Type: Grant
    Filed: November 1, 1996
    Date of Patent: September 23, 1997
    Assignee: Varian Associates, Inc.
    Inventors: Martin John Fennell, Craig Clark Hodges
  • Patent number: 5662769
    Abstract: A process and solution for cleaning Fe contaminants bound to a metallized semiconductor surface after CMP planarization. The solution comprises a PH buffered solution including hydrofluoric acid and a ligand selected from a group consisting of citrates and EDTA.
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: September 2, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Diana M. Schonauer, Steven C. Avanzino
  • Patent number: 5645675
    Abstract: Technique and apparatus for planarizing microsteps on a substrate by compressing the surface to be smoothed against a frozen layer of an etchant, where the compressive force is sufficient to melt the etchant at the contact edges between said microsteps and said etchant.
    Type: Grant
    Filed: May 12, 1994
    Date of Patent: July 8, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Subhash Gupta
  • Patent number: 5627105
    Abstract: A method for making an improved metal silicide layer on a silicon substrate by plasma bombardment of the substrate with Ne ions to remove the native oxide without damage or significant implantation of Ne atoms into said silicon, depositing a metal layer over the Ne etched surface and then rapidly thermally causing the metal layer to react with the underlying silicon.
    Type: Grant
    Filed: April 8, 1993
    Date of Patent: May 6, 1997
    Assignee: Varian Associates, Inc.
    Inventors: Michelangelo Delfino, Mary E. Day, Wilman Tsai
  • Patent number: 5619148
    Abstract: A novel method and apparatus providing an all digital phase comparator of two binary signals which employs a type of cross correlation of two binary signals and provides a 2bit binary word uniquely representative of phase alignment. The method can be carried out using a pair of flip-flop (FF) circuits, each FF having a docking input and a data input, and where each FF has a delay in series with its data input.
    Type: Grant
    Filed: October 10, 1995
    Date of Patent: April 8, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Bin Guo
  • Patent number: 5572038
    Abstract: A charge measuring system for determining implantation dose in a PI.sup.3 system with means to compensate for current in the charge sensor which does not arise from positive ions arriving on the wafer.
    Type: Grant
    Filed: May 7, 1993
    Date of Patent: November 5, 1996
    Assignee: Varian Associates, Inc.
    Inventors: Terry T. Sheng, Charles B. Cooper, III, Susan B. Felch, Charles E. Van Wagoner
  • Patent number: 5552709
    Abstract: The present invention relates to improving the sensitivity of an NMR system for electrically conductive (polar) NMR samples. Many NMR samples use water or a salt solution of water or other electrically conductive liquid as a solvent for biologically active materials. When such a sample is placed in the probe coil of an NMR spectrometer, electrical losses in the conductive material lowers the Q of the receiving circuit and thereby reduces the sensitivity of the spectrometer. These electrical losses can be greatly reduced by breaking up the current paths within the sample. This can be achieved by a special sample cell that compartmentalizes the sample with electrical insulating material reducing the electrical current paths.
    Type: Grant
    Filed: October 17, 1995
    Date of Patent: September 3, 1996
    Assignee: Varian Associates, Inc.
    Inventor: Weston A. Anderson
  • Patent number: 5511608
    Abstract: A clampless heat exchange station for a semiconductor wafer for use in a vacuum chamber, at pressures from 2 Torr to 30 Torr using commercial grade inert gas. The heat exchange chuck has apertures therethrough in the region where the wafer is to be mounted to serve as a miniature plenum gas to provide equal pressure along the bottom and top sides of the wafer. This configuration avoids chipping and particle deposition and provides improved heat transfer rate and wafer temperature uniformity.
    Type: Grant
    Filed: January 4, 1995
    Date of Patent: April 30, 1996
    Inventor: Trace L. Boyd