Abstract: An optical system has an optical image projected on an analog memory, such as a CCD array, generating analog charge signals in the analog memory. The analog charge signals are processed with an analog to digital converter to generate digital information. The digital information is processed with an integrated circuit frequency domain processor to generate frequency domain information. The frequency domain information can be stored in an output memory and can be communicated to a remote location. An image can be displayed in response to the stored analog image information and in response to the frequency domain information. A machine can be controlled in response to the frequency domain information.

Abstract: An optical system is provided having an analog image memory, an analog refresh circuit, and an analog converter. An optical image is projected on an analog memory, such as a CCD array, generating analog image signal samples in the analog memory. The analog charge signal samples can be shifted in the array and can be processed with an analog to digital converter to generate digital signal samples. The digital signal samples can be processed with a digital processor, such as a digital transform processor to generate frequency domain information. The frequency domain information can be stored in an output memory and can be communicated to a remote location. An image can be displayed in response to the stored analog image signal samples or in response to the frequency domain information.

Abstract: An optical system is provided having an analog image memory, an analog refresh circuit, and an analog converter. An optical image is projected on an analog memory, such as a CCD array, generating analog image signal samples in the analog memory. The analog charge signal samples can be shifted in the array and can be processed with an analog to digital converter to generate digital signal samples. The digital signal samples can be processed with a digital processor, such as a digital transform processor to generate frequency domain information. The frequency domain information can be stored in an output memory and can be communicated to a remote location. An image can be displayed in response to the stored analog image signal samples or in response to the frequency domain information.

Abstract: An improved computer system is implemented with an integrated circuit computer having integrated circuit (IC) memories and using a keyboard input and sound output to communicate with an operator. Provision is made for a dynamic memory with a memory refresh arrangement. Memory refresh is synchronized with computer control signals to minimize contention or conflicts with computer operations and to share control circuitry. Improved control system architecture, computer architecture, and memory architecture are provided that are particularly suitable for operator interaction, integrated circuit data processors, and dynamic memories.

Abstract: Memory technologies for storing filter samples include RAMs and CCDs. Adaptive memory capability and memory servo capability improve memory characteristics. In a RAM embodiment, a detector is used to detect a memory address condition and to control the memory and the memory address register in response thereto. In a CCD embodiment, a detector is used to detect a memory reference signal and to refresh the memory signals in response thereto. Improved memory refresh, memory performance, and memory capacity enhance system characteristics. Improved memory architecture provides advantages of increased speed, lower cost, and efficiency of implementation. Information stored in memory can be scanned out at a rate greater than the addressing rate associated with the memories. This permits higher speed operation with lower cost memories. Use of an output buffer, such as a FIFO, permits normalization of memory clock rates.

Abstract: An improved computer system is provided having an integrated circuit computer, having integrated circuit (IC) memories, and having serial communication between the computer and a keyboard and between the computer and a display. Provision is made for dynamic memories with a memory refresh arrangement. Memory refresh is synchronized with computer control signals to minimize contention or conflicts with computer operations and to share control circuitry. Improved system architecture, computer architecture, and memory architecture are provided that are particularly suitable for dynamic memories and integrated circuit data processors.

Abstract: A kernel processor system having a buffer memory, a kernel memory, and a kernel processor provides improved kernel processing capability. The disclosed arrangement comprises an input circuit generating input information; a buffer memory storing buffered information; a write address circuit generating write addresses; a buffer memory write access circuit writing buffered information into the buffer memory in response to the input information and in response to the write addresses; a read address circuit generating read addresses; a buffer memory read access circuit generating buffered output information in response to the buffered information and in response to the read addresses; a kernel memory storing a kernel of information in response to the buffered output information; a kernel processor generating filtered output information in response to the kernel of information; and a display monitor displaying a filtered image in response to the filtered output information.

Abstract: An improved data processor architecture is provided having integrated circuit (IC) memories. Provision is made for dynamic memories with a memory refresh arrangement. Memory refresh is provided in response to instruction execution, synchronized with computer control signals to minimize contention or conflicts with computer operations and to share control circuitry. An improved memory architecture is provided that is particularly suitable for dynamic memories and integrated circuit data processors.

Abstract: Memory technologies for storing filter samples include RAMs and CCDs. Adaptive memory capability and memory servo capability improve memory characteristics. In a RAM embodiment, a detector is used to detect a memory address condition and to control the memory and the memory address register in response thereto. In a CCD embodiment, a detector is used to detect a memory reference signal and to refresh the memory signals in response thereto. Improved memory refresh, memory performance, and memory capacity enhance system characteristics. Improved memory architecture provides advantages of increased speed, lower cost, and efficiency of implementation. Information stored in memory can be scanned out at a rate greater than the addressing rate associated with the memories. This permits higher speed operation with lower cost memories. Use of an output buffer, such as a FIFO, permits normalization of memory clock rates.

Abstract: An improved transform processing system reduces processing bandwidth with improved processor architectures and improved transform algorithms. A hierarchal arrangement facilitates use of the same coefficients for multiple transforms, particularly when the coefficients have not changed. A detector arrangement is provided for detecting a change condition and then causing the processor to bypass redundant processing operations.

Abstract: A computer system having an improved memory architecture uses a variety of memory speed enhancement features that can be used in combination. For example, the memory is scanned out across memory blocks, unnecessary row addressing operations are detected and eliminated, and the memory is organized to reduce row addressing operations for combinations of instruction accesses interspersed by operand accesses. In a DRAM configuration, unnecessary CAS addressing cycles and RAS addressing cycles are detected and eliminated. A memory address detector circuit in the memory controller determines the nature of the memory cycle; chip select, RAS, or CAS; needed to access stored digital information and deletes unnecessary cycles.

Abstract: A filter display system is provided to improve display operations. Filtering of display information, such as with correlation filters, improves the image and enhances events of interest. High speed filters for filtering on the fly as the image is being refreshed provides improved capability for iteratively and adaptively enhancing an image. Parallel processing channels provide multiple filtering operations simultaneously for improved performance. Iteratively refreshing a display with filtered information as the filtered image is built up permits operator intervention for optimizing filtering operations.

Abstract: An improved analog memory arrangement is interfaced to receive digital signals through a digital to analog converter and is interfaced to output analog signals through an analog to digital converter. Analog refreshing is implemented to reduce degradation of analog signals stored by the analog memory including scale factor refreshing and bias refreshing. The analog memory is particularly suitable for illumination signal processing and for storing display images to be displayed.

Abstract: A filter processor provides improved capabilities and reduced complexity by inputting and processing lower resolution signals and by generating higher resolution filtered signals. In a preferred embodiment; an incremental filter processor generates incremental input signals, performs incremental processing, and generates multi-bit filtered signals. Input signals are received from radar, sonar, seismic, or other sources; are processed by the filter processor to generate filtered signals; and can be post processed by a post processor. In a preferred embodiment, the input circuit is a serial input and parallel output circuit, such as a delay line or a CCD; the filter processor is an incremental fast Fourier transform processor; and the post processor is an incremental frequency domain correlator. Other post processors include a frequency domain integrator and an RSS post processor to convert coherent signal samples to noncoherent signal samples.

Abstract: An adaptive filter system is provided to improve filtering operations. Adaptive logic monitors filtered information to determine when sufficient filtering has been performed to perform outputting, further processing, or other operations. In addition, saturation logic monitors filtered information to detect overflow conditions for compensation thereof. In one configuration, filtering operations are performed iteratively, building up the signal to noise ratio of the signals; where filtered signals are monitored to determine when the filtered signals have reached or exceeded a threshold magnitude, as indicative of sufficient signal to noise ratio enhancement, and to prevent the filtered signals from overflowing.

Abstract: The improved memory system can use various memories, such as CCDs and RAMs. Adaptive memory capability and memory servo capability improve memory characteristics. In a RAM embodiment, a detector is used to detect a memory address condition and to control the memory and the memory address register in response thereto. In a CCD embodiment, a detector is used to detect a memory reference signal and to refresh the memory signals in response thereto. Improved memory refresh, memory performance, and memory capacity enhance system characteristics. Improved memory architecture provides advantages of increased speed, lower cost, and efficiency of implementation. Information stored in memory can be scanned out at a rate greater than the addressing rate associated with the memories. This permits higher speed operation with lower cost memories. Use of an output buffer, such as a FIFO, permits normalization of memory clock rates.

Abstract: A filtering system is provided for acquiring and processing signals using a sampled filter for signal separation and signal enhancement; such as for determing locations, distances, and times in a geophysical exploration system. Signature signals permit mixing and seperation with sampled filters, such as for sharing common circuitry and for increasing the amount of acquired information. A sampled filter, such as a digital correlator, is provided for generating high resolution output data in response to low resolution input data processed with low resolution computation circuits. A real-time time-domain correlator is provided with single-bit resolution computational elements to provide improved correclation filtering. A high speed real-time correlator is provided to enhance signals with copositing-after-correlation and with correlation using a plurality of correlation operators.

Abstract: Microcomputer architecture is provided that facilitates a fully integrated circuit computer on a single integrated circuit chip. The architecture includes use of an integrated circuit ROM for program storage, an integrated circuit RAM or scratch pad memory for alterable operand storage, and integrated circuit logic. Additional architectural features include serial data communication, pulse modulated communication, eight bit instruction bytes, sixteen bit operand words, and shared I/O channels.

Abstract: The present invention is directed to an analog memory for storing digital information in analog signal form. Typically, digital information is stored in digital signal form, where each digital bit is stored in a separate digital memory cell. In accordance with the present invention, an analog memory such as a charge transfer device (CTD), bubble memory, or magnetostrictive memory is used to store analog signals. Each analog signal is representative of a plurality of digital bits, thereby providing storage for a plurality of digital bits in each analog memory cell. Use of such an analog memory in combination with a digital system facilitates a hybrid memory, where digital information is stored in analog signal form.

Abstract: An improved data processor architecture is provided having integrated circuit (IC) memories. Provision is made for dynamic memories with a memory refresh arrangement. Memory refresh is provided in response to instruction execution, synchronized with computer control signals to minimize contention or conflicts with computer operations and to share control circuitry.