Abstract: A syndrome generator generates odd syndromes of a sequence of syndromes and stores the odd syndromes in registers. A syndrome sequencer identifies the register storing the next syndrome of the sequence of syndromes, reads the syndrome from the register, and outputs the syndrome to a sequential polynomial generator. Further, the syndrome sequencer generates an even syndrome by squaring the syndrome read from the register and writes the even syndrome into the same register. Moreover, the syndrome sequencer outputs each syndrome of the sequence of syndromes in sequential order. The sequential polynomial generator generates a locator polynomial in a number of iterations based on the sequence of syndromes received from the syndrome sequencer.

Abstract: A packet switch issues credits to a link partner based on credit values and updates the credit values to indicate credits consumed by the link partner based on packets received from the link partner by the ingress port. Additionally, the packet switch selects credit threshold values corresponding to a transmission period of imminent credit starvation of the link partner and compares the updated credit values with the credit threshold values. The packet switch issues additional credits to the link partner when at least one of the updated credit values has reached a corresponding credit threshold value. In some embodiments, the packet switch also issues additional credits to the link partner during idle transmission periods.

Abstract: A packet switch includes an arbiter that generates an availability signal indicating whether one or more pseudo-ports are available for receiving data. Each pseudo-port identifies one or more output ports of the packet switch. An input port of the packet switch receives data of a data packet, generates a grant request identifying a pseudo-port, and issues the grant request to a grant request filter. The grant request filter determines based on the availability signal whether the grant request is serviceable by the packet switch. If the grant request is a serviceable grant request, the grant request filter issues the grant request to the arbiter. The arbiter can select the serviceable grant request and issue a grant to the input port. The data of the data packet can then be routed from the input port to each output port identified by the pseudo-port.

Abstract: A deskew module of a receiver includes deskew units, each of which includes a data aggregation module for selecting a data rate for receiving symbols of a corresponding data stream. The deskew unit includes a data aggregation module that aggregates a predetermined number of the symbols in one or more clock cycles of a clock signal based on the data rate. The predetermined number of symbols is the same for each data rate selectable by the data aggregation module. The data aggregation module outputs the aggregated symbols to a deskew buffer of the deskew unit in a clock cycle of a clock signal. The deskew buffer deskews symbols received from the data aggregation module and outputs the deskewed symbols.

Abstract: A spread spectrum clock signal generator modulates a reference clock signal based on a spread spectrum frequency profile and includes a phase-lock loop for generating a spread spectrum clock signal by aligning a phase of the modulated reference clock signal with a phase of the spread spectrum clock signal. The spread spectrum clock signal generator also includes a loop modulator for modulating the spread spectrum clock signal based on the spread spectrum frequency profile. Because the spread spectrum clock signal generator modulates both the reference clock signal and the spread spectrum clock signal based on the spread spectrum frequency profile, the spread spectrum clock signal has a non-distorted frequency profile and low phase jitter.

Abstract: A packet switch receives packets at an ingress port, generates enqueue records for the packets, and stores the enqueue records in an enqueue structure. The enqueue record of a packet includes a pass flag for indicating whether a permissive passing rule is applicable to the packet. The packet switch determines a routing order for the packets stored in the ingress port based on the enqueue records and a set of ordering rules including the permissive passing rule. If a packet is blocked in the packet switch, the packet switch identifies an oldest unblocked routable packet stored in the ingress port based on the enqueue records and the set of ordering rules. Further, the packet switch routes the oldest unblocked routable packet through the packet switch. In this way, the packet switch allows the oldest unblocked routable packet to pass the blocked packet in the packet switch.

Abstract: A packet switch includes a flow control circuit for preventing a downstream ingress port of the packet switch from providing a non-posted packet to an upstream egress port of the packet switch when a downstream egress port of the packet switch is congested. As a result, congestion is reduced in the downstream egress port. Additionally, congestion is reduced in an upstream ingress port of the packet switch that receives completion packets in response to non-posted packets output from the upstream egress port and provides the completion packets to the downstream egress port. Because congestion is reduced in the upstream ingress port, latency is reduced for a completion packet received at the upstream ingress port and provided to another downstream egress port of the packet switch in response to a non-posted packet provided from another downstream ingress port to the upstream egress port and output from the packet switch.

Abstract: A clock signal generator includes a phase-lock loop for generating an imaging clock signal having a frequency based on a reference clock signal. The imaging clock signal generator also includes a modulation circuit for determining a number of pixels in a horizontal line of an image to be generated based on the imaging clock signal. The modulation circuit generates a modulation signal based on the determined number of pixels and the clock signal generator spreads the frequency of the imaging clock signal across a frequency range based on the modulation signal. In this way, the clock signal generator reduces electromagnetic interference in the imaging clock signal. In further embodiments, the clock signal generator generates an adjustment signal for adjusting the frequency range based on the frequency of the reference clock signal and the frequency of the imaging clock signal.

Abstract: A communication system includes a transmitter that transmits multiple data streams to a receiver in the communication system. Each of the data streams includes data and a skip ordered set. The receiver includes a deskew unit for each data stream, each of which includes multiple data queues. Each of the deskew units stores symbols of the data stream received by the deskew unit into the data queues of the data unit by distributing the symbols among the data queues. The deskew unit aligns data symbols across the data streams by deskewing symbols stored in the data queues of the deskew units based on skip ordered sets in the deskew units. Moreover, the receiver may deskew more than one symbol per clock cycle.

Abstract: A computing system includes a computer device and a detachable touch screen device. The computer device receives input from a touch screen of a detachable touch screen device when the detachable touch screen device is attached to a touch screen port of the computer device and displays an image on a display device of the computer device based on the input. Further, the detachable touch screen device receives input from the touch screen when the detachable touch screen device is detached from the computer device and displays an image on the touch screen based on the input. In various embodiments, the detachable touch screen device performs a computing function, a communication function, or a media function based on the input to the touch screen when the detachable touch screen device is detached from the computer device.

Abstract: A packet switch includes virtual output queues for mapping data units of data packets from input ports to output ports of the packet switch. The packet switch selects virtual output queues based on old age indicators of the virtual output queues and routes data units mapped at heads of the selected virtual output queues to output ports of the packet switch. Further, the packet switch may identify a data unit of a multicast data packet mapped at the head of more than one virtual output queue and contemporaneously route the data unit to more than one output port. Additionally, the packet switch may update an old age indicator to indicate a virtual output queue is old if the virtual output queue maps an unserviceable data unit of a multicast data packet and the same data unit is mapped at the head of a selected virtual output queue.

Abstract: An error correction code system includes an error correction code generator for generating an error correction code based on a data unit and an error detector for detecting at least one bit error in the data unit based on the error correction code. The error correction code generator includes logic circuits for generating check bits in the error correction code. The error detector includes logic circuits for identifying any data bits of the data unit having a bit error based on the error correction code. The logic circuits in the error correction code generator and the error detector are derived from group codes separated from each other by a hamming distance and having a same population count. The error correction code system may also include an error corrector for correcting error bits in the data unit.

Abstract: A packet switch includes individual route tables for ports of the packet switch. Each route table is associated with a port and individually maps a destination identifier of a data packet received at the port to another port in the packet switch. In some embodiments, the packet switch routes a data packet to an intermediate device based on a destination identifier in the data packet. The intermediate device services the data packet and sends the data packet, which includes the same destination identifier, back to the packet switch. In turn, the packet switch routes the data packet to a destination device based on the destination identifier in the data packet. The destination device terminates the data packet and may further service the data packet. In this way, the packet switch routes the data packet to both the intermediate device and the destination device based on the same destination identifier.

Abstract: A method and apparatus are disclosed for predicting the failure of a functional element of an integrated circuit during operation. The method includes determining whether the functional element of the integrated circuit device is in an idle cycle, elevating the temperature of the functional element above a normal operating temperature, performing a stress test of the functional element while the functional element is in the idle cycle, and indicating that the functional element, if it fails the stress test, is a potential future failing element. The stress test can include simultaneously providing a margining test voltage and a stress clock signal to the functional element while the temperature is elevated or at a normal operating temperature. The stress test is performed in the background, during continuous operation of the integrated circuit device, such that normal operation of the integrated circuit device is not interrupted.

Abstract: A clock circuit includes a phase-lock loop and a holdover circuit. The phase-lock loop generates an output clock signal having a constant frequency based on a loop filter voltage of a loop filter in the phase-lock loop. The holdover circuit generates and stores a digital value indicating the loop filter voltage and generates an analog voltage signal having the loop filter voltage indicated by the digital value. Further, the holdover circuit maintains the output clock signal at the constant frequency during a holdover of the phase-lock loop by regenerating the loop filter voltage based on the analog voltage signal. Because the analog voltage signal is based on the digital value, the voltage of the loop filter does not decay over time during the holdover of the phase-lock loop. As a result, the output clock signal remains at the constant frequency during the holdover of the phase-lock loop.

Abstract: A packet switch including input ports having various input bandwidths initializes credit values for the input ports. An arbiter of the packet switch selects input ports based on the credit values and routes data packets from the selected input ports to a switch fabric of the packet switch. The switch fabric routes data packets from the selected input ports to output ports of the packet switch. Moreover, the arbiter modifies the credit value of each selected input port based on the latency for routing the data packet from the selected input port to the switch fabric. In this way, the arbiter promotes fairness in routing additional data packets through the packet switch. In some embodiments, the switch fabric includes a buffered crossbar and the arbiter modifies credit values of crosspoints in the buffered crossbar based on the latency for routing data packets from the crosspoints to the output ports.

Abstract: A communication system includes a transmitter that transmits multiple data streams to a receiver in the communication system. Each of the data streams includes data and a skip ordered set. The receiver includes a data buffer for each data stream that stores a minimal skip ordered set based on the skip ordered set in the data stream received by the data buffer. Each of the minimal skip ordered sets has a same number of symbols. Additionally, each buffer stores data of the data stream received by the data buffer. The receiver aligns the data among the data buffers based on the minimal skip ordered sets in the data buffers and outputs the aligned data. In this way, the receiver deskews the data in the data streams.

Abstract: A communication system includes a packet switch that routes data packets between endpoint devices in the communication system through virtual channels. The packet switch includes output ports each having a link bandwidth for outputting data packets. Each virtual channel is associated with an output port and is allocated a portion of the link bandwidth of the output port. The packet switch receives a data packet identifying a virtual channel at an input port, selects another virtual channel associated with the input port, routes the data packet through the packet switch, and outputs the data packet from the packet switch by using the selected virtual channel. Additionally, the packet switch may select a reliable transmission protocol, a continuous transmission protocol, or a pseudo-continuous transmission protocol for outputting the data packet from the packet switch. In some embodiments, the packet switch modifies the data packet to indicate the selected virtual channel.

Abstract: A clock generator is disclosed that includes an array of MEMS resonators and a test circuit. The test circuit is operable at start-up to operate one or more of the MEMS resonators to generate test output and analyze the test output to determine whether the operated MEMS resonators meet test criteria. A MEMS resonator is selected that meets the test criteria and its output is used to generate an output clock signal. In addition, the test circuit is operable to analyze the output of the selected MEMS resonator and select a replacement MEMS resonator when the output of the selected MEMS resonator no longer meets the test criteria. The replacement MEMS resonator is then operated and its output is coupled to the output of the clock generator. Thereby, failing and potentially failing MEMS resonators are automatically replaced during operation of the clock generator in its end-use application.

Abstract: A packet switch routes data packets based on both packet headers and data payloads in the data packets. The packet switch receives data packets, identifies a destination port of the packet switch for each data packet based on a packet header of the data packet, and routes the data packet to the destination port. Additionally, the packet switch selects data packets among the data packets received by the packet switch based on the data payloads of the received data packets, identifies a trace port of the packet switch for each selected data packet, and routes the selected data packet to the trace port.