Abstract: Electrostatic discharge and electrical overstress protection circuit is disclosed to include a discharging circuit, a detection circuit and a controller. The controller is operable to sense and compare the output voltage from the detection circuit to a reference voltage. The controller, upon detection of a normal operating condition or an electrical overstress (EOS) situation, is operable to cause the discharging circuit to discharge any excess voltage from the voltage supply to the electrical ground at a safety voltage level. The controller, upon detection of an electrostatic discharge (ESD) event, is operable to cause the discharging circuit to discharge the excess voltage at a second voltage level that is less than the safety voltage level.

Abstract: An ESD protection circuit for over-voltage signal bus is disclosed that includes a diode circuit that is electrically connected to a pseudo power supply circuit. The pseudo power supply circuit includes a pseudo first power supply line coupling to an actual first power supply line having a first voltage supply level and a pseudo second power supply line coupling to an actual second power supply line having a second voltage supply level. The pseudo first power supply line and the pseudo second power supply line are clamped by an ESD clamping circuit such that the ESD protection circuit discharges voltage when an ESD event occurs, and does not interfere with the internal circuit when an over-voltage occurs.

Abstract: A DMA interrupt coalescer processes interrupts received from a DMA channel of a DMA controller by transmitting an interrupt request to an interrupt controller if a coalescing condition is satisfied after receiving one or more delayable interrupts, or transmitting the interrupt request regardless of the satisfaction of the coalescing condition if a non-delayable interrupt is received. The coalescing condition is satisfied if a non-zero period of time has transpired since a first of the one or more delayable interrupts was received, or if a number of the one or more delayable interrupts received exceeds a programmed value.

Abstract: A method and apparatus for testing semiconductor wafers is disclosed in which a test circuit is used that includes a waveform generator. The test circuit can test a single transistor or can test multiple transistors. A testing method is disclosed in which a supply voltage is applied to the waveform generator to produce pulses that are applied to the gate of a transistor to be tested. A bias voltage is applied to the source and drain of the transistor to be tested, and the charge pumping current that is generated at the substrate is then measured. The process can be repeated at different bias voltage levels to obtain additional current measurements, indicating the maximum charge pumping current for the transistor that is being tested. The determined maximum charge pumping current can then be used for determining whether there is excessive 1/f noise in the device under test.

Abstract: A base address matching device and method are disclosed. In a switching device having a plurality of input/output ports, a routing device has been described that has an array of registers in which each register holds content associating an address with one of the input/output ports in the switching device and elements of the content in the array of registers are pre-sorted into a specified order, and an address matching element that has a plurality of comparators that are electrically coupled to selected registers in the array of registers. The base address matching element is able to select a matching address from the content of the array of registers and to direct a communication packet to one of the ports in the switch by matching the target address in the packet to an address in the content of the register in the array of registers associated with the port.

Abstract: A photomask and a method for forming a photomask are disclosed in which the photomask pattern is modified to bridge features that are likely to produce electrostatic discharge related defects. In one embodiment those adjacent features that are closely spaced together and have a high surface area differential, are bridged using a bridge that has a width less than the minimum optical resolution of the photolithography process.

Abstract: A charge recycling integrated circuit and a method for integrated circuit charge recycling. In one aspect, a charge storage collector is interposed between a high voltage supply or a low voltage supply and a function block of the integrated circuit. The charge collector is operable to selectively store a charge dissipated in the function block when the logic circuitry of the function block switches between a high voltage value and a low voltage value. The dissipated charge resulting from the switching in the logic circuitry of the function block is selectively stored to the charge collector and the charge collector selectively returns the charge stored on the charge collector to the high voltage supply, the low voltage supply or to another node in the integrated circuit as appropriate.

Abstract: A self-biased electrostatic discharge (ESD) protection circuit for protecting an integrated circuit operating in a normal voltage range that includes both positive and negative voltage levels is disclosed. The self-biased ESD protection circuit includes an input connection for receiving an input voltage, a protection transistor electrically coupled to the input connection, and an electrical sink. The protection transistor is operable to provide ESD protection from the input connection to the electrical sink. The self-biased ESD protection circuit also includes a metal oxide semiconductor (MOS) biasing network electrically coupled to the input connection and the protection transistor. The MOS biasing network is operable to cause the protection transistor to remain in a non-conductive state when the input voltage is in the normal operating voltage range.

Abstract: A current mode driver generates a differential output signal that has a constant voltage swing between a lower voltage level and an upper voltage level. A feedback module determines an intermediate voltage between the lower voltage level and the upper voltage level, compares the intermediate voltage with a reference voltage, and generates a control signal based on a result of the comparison. The current mode driver maintains the voltage swing of the differential output signal at a constant voltage based on the control signal. The differential output signal may have a data signal component and a pre-emphasis signal component.

Abstract: The present invention relates to a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a conductive layer of the gate structure. A layer of titanium nitride is deposited and a rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure.

Abstract: An automated ball mounting system is disclosed In which solder balls are tested by heating the solder balls to a temperature between the eutectic temperature of lead-tin and the melting temperature of a lead free solder ball. If the heated solder balls melt they are standard solder balls. If they do not melt they are lead free solder balls. Solder balls that are input into the automated ball mounting process are automatically tested to determine solder ball type. When the test indicates that the wrong type of solder ball is being used an error message is indicated and the solder ball mounting process stops.

Abstract: An automated ball mounting process is disclosed in which solder balls are tested by heating the solder balls to a temperature between the eutectic temperature of lead-tin and the melting temperature of a lead free solder ball. If the heated solder balls melt they are standard solder balls. If they do not melt they are lead free solder balls. Solder balls that are input into the automated ball mounting process are automatically tested to determine solder ball type. When the test indicates that the wrong type of solder ball is being used an error message is indicated and the solder ball mounting process stops.

Abstract: A memory unit includes a memory organized into protected and non-protected areas. A controller manages access to the memory so that the protected area can be written to through a JTAG or CPU interface. Once written to, the protected area is only accessible to particular logic and cannot be over-written until the entire memory is erased. The controller is configured to allow a BCV to be stored in the memory through either the JTAG or CPU interface. The controller is also configured to allow writing to the protected area and boot configuration vector in memory before CPU boot-up by using a JTAG clock signal provided through an external pin when a system clock signal is not available. A reset circuit generates one or more initialization signals using either the BCV from memory or another BCV provided on external BCV pins, depending upon whether another external BCV pin is asserted.

Abstract: An input buffer circuit includes a voltage limiting circuit and a protection circuit coupled between a pull-up component and a pull-down component of a level detecting circuit. The voltage limiting circuit receives an input signal at a first voltage range and limits the input signal to a safe voltage range, the first voltage range being between an electrical ground and a first supply voltage level, and the safe voltage range being between the electrical ground and a second supply voltage level. The level detecting circuit has a pull-up component receiving the input signal directly from the input terminal and a pull-down component receiving the safe voltage range from the voltage limiting circuit. The level detecting circuit transitions the input signal from the first voltage range to the input signal at the second voltage range. The protection circuit is coupled in series between the pull-up component and the pull-down component so as to protect the level detecting circuit from gate oxide overstress.

Abstract: A photomask and a method for forming a photomask are disclosed in which die regions that define features for a process step of a semiconductor fabrication process are formed on a photomask and a test pattern for a different process step is formed in a blading area of the photomask. Also, a method for forming test structures is disclosed in which the photomask is exposed to transfer the test pattern to a semiconductor substrate. The process step that is associated with the test pattern is then performed, forming a test structure on the semiconductor substrate. By utilizing blading areas of photomasks and including test patterns for different process steps on the same photomask, more test structures can be obtained, without the need to generate additional photomasks for testing purposes.

Abstract: A dual-port Static Random Access Memory (SRAM) cell is disclosed that includes a storage element that is operable to store a data bit and a complement data bit. The dual-port SRAM cell further includes read access circuitry dedicated exclusively to a read operation and write access circuitry dedicated exclusively to a write operation. The read operation and the write operation are performed in a staggered manner. With the read operation performed exclusive on one port and the write operation performed exclusively on the other port of the SRAM cell, smaller transistors can be used to reduce the size of the SRAM cell.

Abstract: A processor access module receives a data command from an agent located externally of a computing processor and performs a cache operation on a cache memory in the computing processor based on the data command. Alternatively, the processor access module receives a data command from the agent and performs a cache operation on the cache memory based on the data command to store a computer program into the cache memory. The processor access module then receives a boot command from the agent and boots the computing processor to initiate execution of the computer program.

Abstract: Methods for determining tolerances are disclosed that can be used for determining whether a lot of semiconductor wafers needs to be reworked. Overlay tolerance, critical dimension tolerance and a dynamic line edge placement tolerance are determined using error measurements that are taken from sample wafers in the lot, giving tolerances that reflect the error state of that particular lot of semiconductor wafers.

Abstract: A package for a flip-chip integrated circuit device and a packaged flip-chip integrated circuit device that include ground strips and power strips disposed on the top surface of the package substrate. Decoupling capacitors are disposed over and electrically coupled to a ground strip and are disposed over and electrically coupled to a power strip. Microvias electrically couple the power strips to a power plane and electrically couple the ground strip to a ground plane. Each power strip and ground strip extend within a die attach region of the package substrate such that a semiconductor die can be bonded thereto for coupling power and ground between the semiconductor die and the decoupling capacitors. The power strip and ground strip provide low impedance pathways between the flip-chip semiconductor die and the decoupling capacitors. Thereby, effective decoupling capacitance is provided that is suitable for high frequency applications.

Abstract: A data transmitter pre-emphasizes the amplitude and frequency bandwidth of a data signal. A data tap generator delays the data signal to generate multiple data tap signals, each of which is delayed by an integer multiple of a data period. A delay module further delays one of the data tap signals by a delay time that is less than the data period to generate a delayed data signal. The delay time of the delayed data signal determines a frequency bandwidth pre-emphasis for the data signal. A filter module multiplies the amplitudes of the data tap signals and the delayed data signal by coefficients to generate signal components of a pre-emphasized data signal. The coefficients of the filter module determine the amplitude pre-emphasis for the data signal. The filter module sums the signal components to generate the pre-emphasized data signal, which includes both the frequency bandwidth pre-emphasis and the amplitude pre-emphasis.