Patents Represented by Attorney Glen B. Choi
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Patent number: 7823041Abstract: Techniques are described herein that can be used to decode signals received over multiple channels. The received signals may be processed using noise reducing logic. Signal-to-noise ratio information per channel for signals received over each of the multiple channels may be considered to determine reliability information concerning the slicer input for each channel. Low density parity check codes or other forward error correction (FEC) codes may be used to decode the processed signals from all the multiple channels based on the reliability information.Type: GrantFiled: September 18, 2006Date of Patent: October 26, 2010Assignee: Intel CorporationInventors: Amir Mezer, Harry Birenboim
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Patent number: 7805657Abstract: Techniques are described that can be used to identify a defective communication channel in a communications network. A decoder in a receiver may decode a signal received from a network. The decoded signal may be re-encoded and compared with the signal received from the network. A count of differences between the re-encoded signal and the signal received from a network may be provided. An indication of errors remaining after the decoding may also be provided. Based on the count and the indication, a defect in the communication channel may be identified. A user may be notified and/or actions may take place.Type: GrantFiled: July 10, 2006Date of Patent: September 28, 2010Assignee: Intel CorporationInventors: Elizabeth Kappler, Patrick Connor, Matthew Jared, Scott Dubal, Duke Hong
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Patent number: 7801299Abstract: Techniques are described herein to overlay and merge any number of tables of equivalent size and structure. Bits or patterns of bits that are similar among tables may be set to a voltage value representative of respective logical ‘0’ or ‘1’. The bits that are different among the tables may be connected to either the value of a table selection signal or its inverse.Type: GrantFiled: September 22, 2006Date of Patent: September 21, 2010Assignee: Intel CorporationInventors: Gunnar Gaubatz, William C. Hasenplaugh, Bradley A. Burres, Wajdi Feghali, Kirk Yap
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Patent number: 7760830Abstract: Techniques are described that can be used to reduce noise attributable to jitter in a received signal. Multiple filters may be available. The number of available filters may correlate to a period of channel-related jitter in terms of clock cycles. One of the filters may be activated for a particular clock cycle. The activated filter may provide a noise reducing signal based on a reference signal and error identified in a received signal. A filter may be used to provide a signal to reduce noise attributable to error signals from interleaved jittered channels.Type: GrantFiled: October 19, 2006Date of Patent: July 20, 2010Assignee: Intel CorporationInventor: Ehud Shoor
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Patent number: 7720854Abstract: Techniques are described herein that can be used to access entries in a packed table. An unpacked table includes empty and filled elements. Filled elements can be accumulated and included in a packed table. An element in the packed table can be accessed by considering the location the element would have been located in the unpacked table. The location can be used to determine the location of the element in the packed table.Type: GrantFiled: August 25, 2006Date of Patent: May 18, 2010Assignee: Intel CorporationInventor: Makaram Raghunandan
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Patent number: 7710968Abstract: A first logic offloads some network protocol unit formation tasks to a second logic. The first logic may request that data be transmitted using a Direct Data Placement (DDP) compatible network protocol unit. The first logic may provide the data as well as other information relevant to forming the DDP compatible network protocol unit. The second logic may form portions of the DDP compatible network protocol unit using the data and the provided information.Type: GrantFiled: May 11, 2006Date of Patent: May 4, 2010Assignee: Intel CorporationInventors: Linden Cornett, Steven King, Sujoy Sen, Parthasarathy Sarangam, Frank Berry
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Patent number: 7693501Abstract: Techniques are described that can be used to reduce interference in a desired channel by one or more other channels. A radio includes a level detect logic that is responsive to both the frequency offset and amplitude of undesired signals and sets the gain applied to received signals based on the offset frequency and determined amplitude of undesired signals. For example, detection of a signal amplitude in an interfering signal in a channel adjacent to the desired channel may be made. Detection of a signal amplitude in an interfering signal in a channel other than the adjacent channel and desired channel may also be made. Based on detection of one or more interfering channel, a gain of an input signal may be adjusted. Interference arising from at least spectral re-growth of noise and clipping noise may be reduced.Type: GrantFiled: December 21, 2006Date of Patent: April 6, 2010Assignee: Intel CorporationInventors: Nicholas Cowley, David Sawyer, Isaac Ali
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Patent number: 7184416Abstract: Techniques are provided for reducing the magnitude of echo tails in a near-end modem. The invention may use an echo tail canceller to generate a signal that cancels echo tail. One characteristic of the echo tail canceller may be determined during a time when only the near-end modem is scheduled to transmit signals. Another characteristic of the echo tail canceller may be determined at approximately the time that a body echo canceller has reached convergence and may be re-determined periodically thereafter. The near-end modem may subtract from any received signal an echo tail canceller signal generated by the echo tail canceller to cancel echo tail from the received signal.Type: GrantFiled: May 22, 2002Date of Patent: February 27, 2007Assignee: Intel CorporationInventors: Amod V. Dandawate, Qian C. Xie, Huaiyu Zeng
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Patent number: 7158631Abstract: Techniques to cancel echo utilizing reduced die space and reduced usage of a time shared processor.Type: GrantFiled: October 30, 2002Date of Patent: January 2, 2007Assignee: Intel CorporationInventors: Huaiyu Zeng, Chunming Han
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Patent number: 7154977Abstract: A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR may receive an input signal that suffers from jitter. PR may generate a phase matched signal having substantially the same phase as that of the input signal. To generate the phase matched signal, PR may use a clock signal provided by a single side band oscillator, CMU, or a clock signal having substantially the same level of jitter as that of the input signal to generate the phase matched signal. FIFO may sample the phase matched signal and store such samples. CMU may request and output samples from the FIFO at a frequency determined by a reference clock signal.Type: GrantFiled: March 31, 2003Date of Patent: December 26, 2006Assignee: Intel CorporationInventors: Casper Dietrich, Steen B. Christensen
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Patent number: 7151813Abstract: A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR may receive an input signal that suffers from jitter. PR may generate a phase matched signal having substantially the same phase as that of the input signal. To generate the phase matched signal, PR may use a clock signal provided by a single side band oscillator, CMU, or a clock signal having substantially the same level of jitter as that of the input signal to generate the phase matched signal. FIFO may sample the phase matched signal and store such samples. CMU may request and output samples from the FIFO at a frequency determined by a reference clock signal.Type: GrantFiled: July 17, 2002Date of Patent: December 19, 2006Assignee: Intel CorporationInventor: Casper Dietrich
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Patent number: 7151379Abstract: Briefly, a system that may facilitate system and line loop back diagnostic operations. In one possible implementation, a first transceiver may transmit test signals to a second transceiver. The second transceiver may include a transmitter with the capability to reduce jitter in received test signals prior to transmission of received test signals back to the first transceiver. The first transceiver may determine path integrity characteristics based on the test signals transmitted from the second transceiver.Type: GrantFiled: September 9, 2003Date of Patent: December 19, 2006Assignee: Intel CorporationInventor: Steen Bak Christensen
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Patent number: 7136444Abstract: A signal regenerator that reduces noise in a reference clock signal. In one possible implementation, phase comparisons between the reference clock signal and an input signal are made. Based on the phase comparisons, phases of a clock signal having a lower frequency than the reference clock signal are adjusted. Phases of the phase adjusted lower frequency clock signal are compared with phases of a divided down version of the reference clock signal. Based on such comparisons, phases of the reference clock signal may be adjusted.Type: GrantFiled: July 25, 2002Date of Patent: November 14, 2006Assignee: Intel CorporationInventors: Steen B. Christensen, Casper Dietrich
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Patent number: 7119701Abstract: An apparatus and method for detecting a connection to a data transmission network functions by detecting the network signal energy on a network cable while avoiding the problems of excessive power consumption and generation of excessive electrical noise. By monitoring the receive network lines and determining if there is electrical energy on the cable in the form particular to the type of network supported by the network adaptor card, the host computing device can power-down the transceiver associated with the network adaptor card until an active network connection is detected.Type: GrantFiled: February 2, 2005Date of Patent: October 10, 2006Assignee: Intel CorporationInventor: Kurt R. Browning
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Patent number: 7098047Abstract: Briefly, test wafer reuse techniques.Type: GrantFiled: November 19, 2003Date of Patent: August 29, 2006Assignee: Intel CorporationInventor: Kramadhati V. Ravi
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Patent number: 7078912Abstract: Briefly, techniques that may be used to provide characteristics of a signal propagation medium. Based on test signals transmitted into the medium, the techniques may be used to construct a mosaic waveform with multiple time segments. Each time segment may be based on a gain enhanced received reflected signal and each time segment may have an applied gain that is at a highest level without causing saturation. The techniques may further remove unwanted bridge tap reflection.Type: GrantFiled: June 6, 2003Date of Patent: July 18, 2006Assignee: Intel CorporationInventor: Chunming Han
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Patent number: 7072430Abstract: Briefly, an oscillator device with impedance elements to prevent premature improper biasing of transistor nodes and to increase the maximum possible peak-to-peak signal swing.Type: GrantFiled: August 2, 2005Date of Patent: July 4, 2006Assignee: Intel CorporationInventor: Kenn Christensen
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Patent number: 7054331Abstract: A technique for de-skewing a group of serial data signals respectively outputted from a group of data lanes includes simultaneously feeding a test signal to inputs of the group of data lanes and monitoring respective outputs thereof. A predetermined data element of the test signal outputted from each of the group of data lanes is respectively detected and respective elapsed times from the detection of the predetermined data element outputted from each of the group of data lanes to the detection that the predetermined data element has been outputted from all of the group of data lanes are measured. The group of serial data signals are then de-skewed by respectively delaying them in accordance with their respective measured elapsed times. The test signal may include the predetermined data element, a lane identifier, and a predetermined number of additional data symbols, the predetermined data element being a predetermined data character.Type: GrantFiled: September 13, 2000Date of Patent: May 30, 2006Assignee: Intel CorporationInventors: Dean S. Susnow, Richard D. Reohr, Jr.
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Patent number: 7032392Abstract: A method and apparatus for cooling an integrated circuit die. An integrated circuit package comprises an integrated circuit die. A cooling fluid makes contact with the integrated circuit die. In one embodiment, an interposer is disposed between the integrated circuit die and a package substrate. The integrated circuit die and/or the interposer may have microchannels in its surface.Type: GrantFiled: December 19, 2001Date of Patent: April 25, 2006Assignee: Intel CorporationInventors: Paul B. Koeneman, Mark A. Trautman
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Patent number: 7032035Abstract: In some embodiments, a method is provided for transmitting packet headers in a network adapter across a network. In this embodiment memory protocol headers and application data into packet buffers are stored on a host. On the network adapter a MAC header storing in a cache. The stored packet buffers and stored MAC header are transmitted across a network thereby reducing DMA requests.Type: GrantFiled: December 8, 2000Date of Patent: April 18, 2006Assignee: Intel CorporationInventor: Daniel R. Gaur