Abstract: Techniques for performing credit-card transactions without disclosing the subject matter of the transaction to the institution providing the credit card. The techniques include the use of a communications exchange so that information and funds may be transferred without the destination for the transfer knowing the source of the information or funds and the use of public key encryption so that each party to the transaction and the communications exchange can read only the information the party or the exchange needs for its role in the transaction. Also disclosed are techniques for authenticating a card holder by receiving personal information from the card holder, using the information to ask the card holder one or more questions, and using the answers to authenticate the card holder.

Abstract: Apparatus and methods for integrating a knowledge base management system with a data base system. The knowledge base management system employs compositional descriptions which describe information in terms of concepts. A translation component of the apparatus translates compositional descriptions into data base queries, so that information matching a compositional description may be retrieved from the data base. The translation component further permits display of the retrieved data in terms of the compositional description. The returned information can be automatically integrated into the knowledge base, either item by item or on the basis of the compositional description which was used to return the information.

Abstract: A lottery system using a public switched network to enter a lottery and to receive an indication of winning while connected on a lottery call. A lottery customer dials a telephone number to enter the lottery. The customer has his eligibility verified by a credit card number or the telephone number of the calling station. The customer is then prompted to speak or key a lottery entry which may be a full number, partial number, or an indication that a lottery comparison number is to be generated by a lottery processor. From the customer's lottery entry, a lottery comparison number is generated. This is compared with a random lottery target number generated by the lottery processor. If the comparison number and target number match, the customer is informed of his winning. Advantageously, lottery customers are quickly notified of their winnings.

Abstract: A knowledge-based artificial intelligence system which provides design advice. The artificial intelligence system includes a knowledge base of design information. Users of the system indicate an area about which they require design advice. The system provides the relevant advice. Included in the advice is an indication of the "owner" of the advice. The advice and the relationship between the design made by the user are part of a trace of the users' session with the system. The trace becomes part of a design document for the design. When the design is reviewed, the trace is reviewed as well. The system includes an interface for updating the knowledge base, and if the design review indicates a need to correct the knowledge base, the corrections are made using the interface for updating. A preferred embodiment of the system is used to provide advice to designers of a large software system concerning the use of an error reporting and handling system in the system being designed.

Abstract: An ISDN modem. The modem includes an independent clock which controls the modem's input and output filters and two dependent clocks whose rates are functions of the independent clock and which are synchronized with external timing signals. When a dependent clock is synchronized, timing adjustment signals to other components of the modem specify the type and direction of synchronization. One of the dependent clocks and the independent clock are used to control a decimator which provides two samples of a symbol which are one independent clock cycle apart. One of the samples is a primary sample from which the symbol is interpreted and the other is a secondary sample which is used to continually train a jitter canceller. When a clock is synchronized, the secondary sample becomes the primary sample, providing the modem with a time-invariant echo path. On clock synchronization, the jitter canceller responds to the timing adjustment signals by providing adaptation information to the linear echo canceller.

Abstract: A low-cost, low-power infrared digital communications system. The system overcomes the problem of infrared noise from interior lighting without using either a high-power infrared source or upmodulation of the source. The system includes an infrared collector which uses a non-directional concentrator to concentrate the infrared radiation and a circuit which detects the digital infrared signal in the noise by detecting the edges of the digital infrared signal. Devices in the system need not be aimed at each other, but need only be in line of sight of each other. The preferred embodiment employs the digital infrared signals to communicate between a set of digital devices and a breaker box connected to the telephone network.

Abstract: Methods and apparatus for employing a communications system with actively connects communicating entities to mediate transactions. Disclosed are general methods and apparatus for mediating transactions, methods and apparatus permitting information from one transaction to be used in other transactions, and methods and apparatus for performing credit card transactions in which the vendee need not disclose his credit card to the vendor. An implementation of a system for performing credit card transactions in a stored program-controlled telephone switching network is also disclosed.

Abstract: A processor which is specially adapted for use as a coprocessor. The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain output pins have three-state bus drivers which employ feedback to ensure that a signal on a line being driven by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline.

Abstract: A processor specially adapted for use as a coprocessor. The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain output pins have three-state bus drivers which employ feedback to ensure that a signal on a line being driven by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline.

Abstract: A packet switch of the type in which packets received in the switch are stored in memory until they are output. In the switch fabric of the switch, packets are serially received in input shift registers wide enough to store an entire packet, output in parallel to memory which is as wide as the input shift register, moved in parallel in the memory, and output in parallel to an output shift register. The bus connecting the input shift registers, the output shift register, and the memory is as wide as the input shift register, but does not cross the boundaries of the semiconductor chips making up the switch fabric, thus avoiding the electrical problems of very wide buses. In the disclosed implementation, there are 14 input lines and 14 output lines. A switch memory is associated with each output line and receives packets from all 14 input lines, accepting only those destined for the output line associated with the input line.

Abstract: A processor specially adapted for use as a coprocessor The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain outputs pins have three-state bus drivers which employ feedback to ensure that a signal on a line being driven by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline.

Abstract: Apparatus and methods for time multiplexing a resource among a plurality of entities at average rates and with deterministic delays between accesses to the resource by an entity. An entity accessing the resource receives a time slot on the resource; a fixed number of time slots constitute a frame. Each entity receives a fixed allocation of time slots in the frame. When an entity has work for the resource to do, it receives access to the resource for a number of slots in each frame equal to the lesser of the number of slots required to do the work and the number of slots in the allocation. A rate-controlled server is disclosed which defines a frame and allocations therein, as well as a hierarchy of servers which combines rate-controlled traffic with best effort traffic. In the hierarchy, a rate-controlled server activates a round-robin server when the entities served by the rate-controlled server do not require all the slots in a frame.

Abstract: Apparatus and method for performing an application-defined operation on data as part of a system-defined operation on the data. The apparatus and method are embodied in a distributed transaction processing system in which processes running on component systems which may be heterogeneous interact according to the client-server model. In the apparatus and method, a type is associated with the data and application-defined operations which are part of certain system-defined operations are defined for each type. The system-defined operations which the application-defined operations are part of include allocation, reallocation, and deallocation of buffers and sending buffers between clients and servers using remote procedure calls. In the allocation and reallocation operations, the application-defined operation is initialization; in the deallocation operation, it is uninitialization.

Abstract: A testable implementation of a given finite state machine is produced by defining a test finite state machine which can set and read the same number of flip flops as are required for the memory elements of the given finite machine and then merging the test finite state machine with the given finite state machine to produce a testable finite state machine in which the test finite state machine and the given finite state machine share the flip flops. The testable implementation is then produced from the testable finite state machine. Since the test finite state machine and the given finite state machine share the flip flops of the testable implementation, the test finite state machine can be used to test the given finite state machine by setting and reading the given finite state machine's flip flops. Techniques are further disclosed for defining the test finite state machine and merging the test finite state machine with the given finite state machine.

Abstract: A target which is a good conductor of heat and electricity is plasma sprayed with a weakly conducting material such as a metallic oxide. The target is then employed in a magnetron sputtering apparatus to sputter the material sprayed onto the target onto a substrate. The technique permits use of power densities and target sizes and shapes which are advantageous for sputtering substrates having large surface areas.

Abstract: An interactive image editor. Editing commands are interactively imputted to a computer by a user to form an image transformation function. The commands define how to alter the pixels of the image and the portions of the image to alter. The editor parses the commands and generates a program for performing the image transformation. The program is then executed, either by interpreting it or by first compiling it on-the-fly. In either case, each affected pixel of the image is transformed in accordance with the command statements.

Abstract: Apparatus for compensating for the effect of a local condition on an active element in a portion of an integrated circuit. The apparatus includes a detecting element in the portion of the integrated circuit which is subject to the local condition and produces a response to the local condition which is proportional to the local condition's effect on the active element and a compensation element which is coupled to the detecting element and to the portion for reacting to the response of the detecting element tot he local condition by providing a compensating input to the portion which is proportional to the response and which compensates for the local condition's effect on the active element. An embodiment of the apparatus which compensates for leakage currents in FETs in a dynamic CMOS integrated circuit employs one or more FETs which are interspersed among active FETs as the detecting element and a current mirror as the compensating element.

Abstract: Instruction prefetching apparatus particularly adapted to executing an EXECUTE instruction specifiying a single subject instruction. The apparatus includes a first and second separately-controllable instruction syllable register and control apparatus. Under control of the control apparatus, the first instruction syllable register receives only the first syllable of the prefetched instruction; the second instruction syllable register receives all other syllables. The instruction syllable registers may be loaded either directly from memory or from a data register internal to the CPU. In the first case, the address of the instruction syllable to be prefetched is contained in a special instruction address register which is incremented each time an instruction syllable register is loaded. In the second case, the loading does not affect the value of the instruction address register.

Abstract: An optical fiber switch in which a switchable fiber is switched to a first position by a first member inside the housing made of a shape memory material. This first member attempts to restore itself to an original shape heated above a first temperature and, in so doing, exerts a switching force on the switchable fiber. In a preferred embodiment, biasing means push the switchable fiber into a second position when the first means is below a second temperature. The first member exerts a force on the switchable fiber in a direction opposite to that of the biasing means of sufficient force to overcome the biasing force when the first member is above the first temperature. When the shape memory member is cooled, it assumes a distorted shape which allows the biasing means to control the position of the switchable fiber. In one embodiment, the biasing means is a second member also made of a shape memory material.

Abstract: A method for administering secure access to files of a computer system. For a process-file pair, a first security label associated with the process is compared with a second security label associated with the file in response to a request to read or write the file. If the security label of the destination (file or process) of the read or write operation does not dominate the security label of the source (file or process), the security label of the destination is dynamically raised accordingly. If the security label of the file or process is raised, an indicator associated with this process and with this file is set to a first state representing that the file is safe for this process-file pair. Indicators associated with every other process linked with this file are set to a second state representing that the file is unsafe for those process-file pairs.