Abstract: A semiconductor integrated circuit includes first to eighth column selection transistors and ninth to twelfth column selection transistors. The ninth column selection transistor is connected to the first and second column selection transistors. The tenth column selection transistor is connected to the third and fourth column selection transistors. The eleventh column selection transistor is connected to the fifth and sixth column selection transistors. The twelfth column selection transistor is connected to the seventh and eighth column selection transistors. A first column selection line is connected to gates of the first, third, fifth and seventh column selection transistors. A second column selection line is connected to gates of the second, fourth, sixth and eighth column selection transistors. Third to sixth column selection lines are connected to gates of the ninth to twelfth column selection transistors, respectively.

Abstract: A semiconductor wafer on which elements have been formed is diced and a rear surface of the semiconductor wafer is ground by a dicing before grinding method to form discrete semiconductor chips. The discrete semiconductor chips are adhered to an adhesive film and then the surface of the adhesive film is removably affixed to a dicing tape. After this, any excess portions of the adhesive film disposed between the respective semiconductor chips are removed.

Abstract: Disclosed and claimed are: a composition including at least one glycosaminoglycan, e.g., CIS, at least one perfluorinated substance and at least one alginate, e.g., sodium alginate, wherein: the at least one glycosaminoglycan and/or the perfluorinated substance and/or the alginate are cross-linked or polymerized, e.g., the alginate is cross-linked or polymerized, for instance by addition of an inorganic salt, such as a calcium salt; or the at least one glycosaminoglycan, the perfluorinated substance and the alginate are covalently bound, e.g., by means of a coupling reaction involving a linker molecule such as DVS; or the at least one glycosaminoglycan and/or the perfluorinated substance and/or the alginate are cross-linked or polymerized, e.g., the alginate is cross-linked or polymerized, for instance by addition of an inorganic salt, such as a calcium salt, and the at least one glycosaminoglycan and the alginate are covalently bound, e.g.

Abstract: A semiconductor device includes a first insulating film comprising an opening, a capacitor formed at a selected position in the opening, a second insulating film formed at least in the opening, and a third insulating film formed on the second insulating film.

Abstract: A level shifter comprises a latch circuit, a first capacitor and a second capacitor. The latch circuit has a first node and a second node set to a first voltage or a second voltage. The second node is set to the second voltage when the first node is set to the first voltage and the second node is set to the first voltage when the first node is set to the second voltage. A first terminal side of the first capacitor is connected to the first node. A first signal is supplied to a second terminal side of the first capacitor. A third terminal side of the second capacitor is connected to the second node. When the first signal is supplied to the second terminal side of the first capacitor, an inverted replica of the first signal is supplied to a fourth terminal side of the second capacitor.

Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Abstract: There is provided a semiconductor memory device, which realizes rewriting of data in the memory cell by applying a potential difference between the gate and the source, or applying a potential difference between the gate and the drain, which is larger than the power supply voltage. This semiconductor memory device is provided with a source line potential control circuit configured to control the source line potential. The source line potential control circuit sets the source line potential at the time of the mode for programming “1” data in a plurality of blocks in one package to a level lower than at the normal data programming mode.

Abstract: There is disclosed a semiconductor integrated circuit device comprising a memory cell array, row decoder, sense amplifier, column gate with two or more stages connected in series, column gate driving circuit, data latch, multiplexer, and address control circuit, and the multiplexer sequentially selects data corresponding to a predetermined address from a plurality of data latched by the data latch. The address control circuit reverses a driving signal for driving at least one stage of the column gate with two or more stages connected in series and selects the columns designated by the next selected plurality of addresses, while the multiplexer sequentially selects the data corresponding to the predetermined address.

Abstract: An apparatus for treating a substrate which includes a chamber and an opening formed in the chamber allowing the substrate to be conveyed into the chamber or taken out thereof. The chamber, also, includes a detachable baffle plate that fits around an electrode. For treatment to commence, the substrate is placed on the electrode and the chamber is exhausted of or supplied with gases. The electrode is then vertically lifted together with the baffle plate and the baffle plate is moved either to a position that is higher in level than an upper end of the opening of the chamber or to a position that is lower in level than a lower end of the opening of the chamber. This allows the baffle plate to shield a region near the opening of the chamber from a treatment region and allows reaction products to be adhered to the baffle plate.

Abstract: The present invention relates to a vector for expression of a heterologous protein by a Gram negative bacteria, wherein the vector includes a nucleic acid such as DNA encoding the following: an origin of replication region; optionally and preferably a selection marker; a promoter; an initiation region such as translation initiation region and/or a ribosome binding site, at least one restriction site for insertion of heterologous nucleic acid, e.g. DNA, encoding the heterologous protein, and a transcription terminator. The inventive vector may contain DNA encoding the heterologous protein, e.g., pro-insulin such as pro-insulin with a His tag.

Abstract: The semiconductor memory includes a memory cell which handles a clock signal, an address fetch and a command circuit. The memory cell is designated by an address signal and stores data. The clock signal is supplied thereto so as to provide timing for an access to the memory cell, and the clock signal has a leading edge and a trailing edge. The address fetch circuit fetches the address signal for designating the memory cell in synchronism with both of the leading edge and trailing edge of the clock signal. The command circuit fetches a command signal for instructing the access to the memory cell in synchronism with both of the leading edge and the trailing edge of the clock signal.

Abstract: Claimed and disclosed is a method of manufacturing a semiconductor device, the method comprising the steps of forming a dummy gate on a semiconductor substrate, forming a source-drain diffusion region by introducing an impurity into the semiconductor substrate having the dummy gate as a mask, removing the dummy gate to form an opening, and forming a gate electrode within the opening with a gate insulating film formed below the gate electrode. The dummy gate is further formed by coating the semiconductor substrate with a polymer having a higher carbon content than hydrogen content so as to form a polymer film, forming a photoresist pattern on the polymer film, and transferring the pattern shape of the photoresist pattern onto the polymer film.

Abstract: Claimed and disclosed is a treatment apparatus for treating a substrate under decompressed atmosphere, comprising: a chamber, an exhausting means for exhausting the chamber, a first electrode provided in the chamber on which the substrate is mounted or held, a second electrode provided in the chamber opposing the first electrode, a liquid supply source containing a liquid material from which a process gas is generated, a housing provided between the liquid supply source and the chamber to be communicated to the liquid supply source and the chamber, a porous heating unit arranged in the housing for generating the process gas by heating the liquid material supplied from the liquid supply source into the housing in order to vaporize the liquid material, a process gas introduction section provided between the housing and the chamber for guiding the process gas from the housing to the chamber and vibrators to vibrate the porous heating unit.