Abstract: A split gate electrode MOS FET device includes a tunnel oxide layer formed over a semiconductor substrate. Over the tunnel oxide layer, a doped first polysilicon layer is formed with a top surface. A native oxide which forms over the doped first polysilicon layer may have been removed as an option. On the top surface of the first polysilicon layer, a silicon nitride layer was etched to form it into a cell-defining layer. A polysilicon oxide dielectric cap was formed over the top surface of the first polysilicon layer. Aside from the polysilicon oxide cap, the first polysilicon layer and the tunnel oxide layer were formed into a floating gate electrode stack in the pattern of the masking cap forming a sharp peak on the periphery of the floating gate electrode. Spacers are formed on the sidewalls of the gate electrode stack. Blanket inter-polysilicon dielectric and blanket control gate layers cover exposed portions of the substrate and the stack.

Abstract: A vertical memory device on a silicon semiconductor substrate is formed by the following steps. Form an array of isolation silicon oxide structures on the surface of the silicon semiconductor substrate. Form a floating gate trench in the silicon semiconductor substrate between the silicon oxide structures in the array, the trench having trench sidewall surfaces. Dope the sidewalls of the floating gate trench with a threshold implant through the trench sidewall surfaces. Form a tunnel oxide layer on the trench sidewall surfaces, the tunnel oxide layer having an outer surface. Form a floating gate electrode in the trench on the outer surface of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Form an interelectrode dielectric layer over the top surface of the floating gate electrode. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode.

Abstract: A method/system for performing dynamic re-scheduling of priorities of work-in-process in a fabrication plant for manufacturing of a product is provided. It reads a key stage report for the work-in-process and a master production schedule for the work-in-process from stored data. It generates a master production schedule report from the key stage report and the master production schedule following only Due_Date data for the work-in-process, and generates a work-in-process distribution matrix for integrating the master production schedule report with work-in-process quantity data within a deliverable cycle time; allocates selected lots from the work-in-process distribution matrix using a snake pattern method to allocate the selected lots from the matrix, and changes the due date for the selected lots of the work-in-process selected by the snake pattern method. It generates a final re-scheduling table for the work-in-process including the selected lots.

Abstract: A longitudinally magnetically biased dual stripe magnetoresistive (DSMR) sensor element comprises a first patterned magnetoresistive (MR) layer. There are contacts at the opposite ends of the patterned magnetoresistive (MR) layer with a first pair of stacks defining a track width of the first magnetoresistive (MR) layer with a first pair of stacks defining a track width of the first magnetoresistive (MR) layer, each of the stacks including a first Anti-Ferro-Magnetic (AFM) layer and a first lead layer. With the first MR layer in place the device was annealed in the presence of a longitudinal external magnetic field. A second patterned magnetoresistive (MR) layer was formed above the previous structure. There are contacts at the opposite ends of the second patterned magnetoresistive (MR) layer with a second pair of stacks defining a second track width of the second patterned magnetoresistive (MR) layer.

Abstract: A method of fabricating integrated circuit wafers, in accordance with this invention comprises the following steps. Provide an integrated circuit wafer having devices formed therein covered with a metal layer and a photoresist layer over the metal layer which is selectively exposed and developed forming a photoresist mask. Introduce the wafer into a multi-chamber system, patterning the metal layer by etching and then exposing the mask to light in a cooled chamber wherein the light is derived from a source selected from a mercury lamp and a laser filtered to remove red and infrared light therefrom before exposure of the wafer thereto. The chamber is cooled by a refrigerant selected from water and liquefied gas. Then remove the wafer, and load it into a photoresist stripping tank to remove the photoresist mask with a wet photoresist stripper. Place the wafer in a batch type plasma chamber after removing the photoresist mask.

Abstract: A charged particle beam system with a source of charged particles produces a beam directed along a path. A given electromagnetic lens is located along the path. The given electromagnetic lens is adapted to produce a first field directed with a first orientation adapted for affecting a beam of charged particles directed along the path through the lens. A bucking electromagnetic lens is juxtaposed with the given electromagnetic lens adapted to produce a bucking field directed with a bucking orientation adapted for affecting the beam of charged particles directed along the path. The bucking field has an orientation opposing the first field. A fringe field from the bucking electromagnetic lens produces a nulling field to compensate for aberrations and/or beam disturbances.

Abstract: This method forms an SRAM device with an array of cells having low resistance conductors for the reference potential (Vss) circuits connected to transistors in the SRAM device. First form an SRAM device with two pull-up transistors, two pull-down transistors and two pass gate transistors, including thin film gate electrode conductors and interconnection lines, each of the transistors having a drain region and a source region with source regions of the two pull-up transistors connected to a power supply voltage (Vcc). Then form a plurality of dielectric and metallization layers over the transistors, the conductors and the interconnection lines. Form a stack of layers over the transistors, the stack of layers comprising a plurality of metallization layers sandwiched between a plurality of dielectric layers. Form a conductive reference potential node electrically connected to the source region of each of the pull-down transistors.

Abstract: A merged read/write magnetic recording head comprises a low magnetic moment first magnetic shield layer over a substrate. A read gap layer with a magnetoresistive head is formed over the first shield layer. A shared pole comprises a low magnetic moment second magnetic shield layer plated on a sputtered seed PLM layer over the read gap layer, a non-magnetic layer plated over the PLM layer and a HMM lower pole layer plated over the second magnetic shield layer. A write gap layer is formed over the first high magnetic moment pole layer of the shared pole. An upper pole comprises a high magnetic moment pole layer over the write gap layer.

Abstract: A method/system is provided for performing a design review checking operation and analyzing the resultant data. Perform a DRC operation describing chip features and generating flags for violation sites including patterns and paths. Execute pattern analysis and grade classification steps for the violation sites. Generate a vector array for each chip feature for each of the violation sites. Compare the vector arrays to determine whether degrees of similarity of geometries of chip features of violation sites meet one of a set of criteria. Classify the violation sites into classes with similar criteria. Select representative arrays from each class of violation sites to provide an output. Calculate distance from a violation site from the origin in a two-dimensional array. Give a grade to each vector array to indicate the level of seriousness of the rule violation by the site. Use a layout viewer to view the error flags generated by pattern analysis and grade classification steps.

Abstract: A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thick floating gate layer of doped polysilicon over the tunnel oxide layer filling the trenches and extending above the trenches. Etch the floating gate layer down below the top of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thick control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes.

Abstract: A method and system provide for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages. The method comprising the following steps. Inspect semiconductor devices on the wafer visually to identify the location of visual defects on dies being manufactured on the wafer and to maintain a count of visual defects on the dies by location. Inspect the semiconductor dies on the wafer to determine the location and number defective dies on the wafer at each of the manufacturing stages. Calculate the defective die count for each stage for the wafer. Calculate the defective bad die count for each stage for the wafer. Determine the percentage of the defective bad die count divided by the defective die count. Plot the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages.

Abstract: A spin valve device comprises a free layer, a spacer layer, a pinned layer, an antiferromagnetic layer, and a patterned underlayer that includes a magnetic material for providing trackwidth and longitudinal bias. The patterned underlayer can comprise a buffer layer, an antiferromagnetic layer and a ferromagnetic layer. Alternatively, the patterned underlayer can comprises a buffer layer, a chromium layer and a hard biasing, permanent magnetic layer which provides trackwidth and longitudinal bias. A lower conductor can be located on the underlayer.

Abstract: A structure with bit lines and capacitors for a semi-conductor memory device is formed by the following steps. Form a gate oxide layer on a doped silicon semiconductor substrate. Form gate electrode stacks juxtaposed with conductive plugs over the gate oxide layer, the conductive plugs being separated by a first dielectric material in a direction oriented transversely of the gate electrode stacks. Form a first interpolysilicon layer above the conductive plugs. Form bit-lines in the first interpolysilicon layer above the first dielectric material. Form a capacitor above a plug and between a pair of the bit-lines.

Abstract: A semiconductor device is formed on a semiconductor substrate with an N-well and a P-well with source/drain sites in the N-well and in the P-well by the following steps. Form a gate oxide layer and a gate electrode layer patterned into a gate electrode stack with sidewalls over a substrate with N-well and P-well. Form N− LDS/LDD regions in the P-well. Form N− LDS/LDD regions in the P-well and P− lightly doped halo regions in the P-well below the source site and the drain site in the P-well. Form a counter doped halo region doped with N type dopant below the source region site in the P-well. Form spacers on the gate electrode sidewalls. Then, form lightly doped regions self-aligned with the gate electrode in the source/drain sites. Form N+ type doped source/drain regions deeper than the N− LDS/LDD regions in the P-well in the source/drain sites. Form P+ type doped source/drain regions deeper than the P− LDS/LDD regions in the N-well in the source/drain sites.

Abstract: An instrument for measurement of illumination intensity distribution of an Electron Beam Projection System (EBPS) comprises a reticle with a clear subfield, a pinhole plate comprising a block of a low atomic number material with a high aspect ratio pinhole therethrough, the pinhole plate being positioned at the image plane of the EBPS. Means is provided for detecting electrons passing through the pinhole, and means is provided for moving, scanning, the pinhole with respect to a fixed electron intensity distribution or scanning the electron intensity distribution with respect to pinhole when held in a fixed position.

Abstract: A system and a method are provided employing the concept of Budget Queue Time to define the priority of lots while distinguishing clearly between the controllable an uncontrollable portions of the remaining production time needed and to make the priority setting further meet the actual status. Two indices X and P are used concurrently to define the priority of a lot. X is the index of the delivery week which indicates the week in which the lot must be out of the fabrication process and P denotes the temporary priority according to the Budget Queue Time, but X is the dominant one of the two indices X and P. Use is made of the concept of remaining Budget Queue Time instead of traditional queue time of current stage for dispatching to reduce the variance of cycle time variance.

Abstract: In forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps, form a trench with a trench line on top and a contact hole on the bottom in the dielectric layer with the overall trench reaching down to the substrate. Preclean the trench. Form a tantalum film over the dielectric layer including the trench walls, covering the exposed the substrate surface. Fill grain boundaries of the tantalum film with at least one of tantalum oxide and tantalum nitride forming a filled tantalum film. Form a redeposited tantalum layer above the filled tantalum film. Form a copper seed film above the redeposited tantalum film. Plate the device filling the trench with a plated bulk copper layer on the seed film. Planarize the device to expose the top surface of the dielectric layer, removing surplus portions of the filled tantalum film, the copper seed film, and the bulk copper layer.

Abstract: A capacitor core is formed on a semiconductor device with a first conductive layer in contact with a plug. A mold is formed from a stack of alternately doped and undoped silicon dioxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Pattern the silicon dioxide layers in the mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in the stack of silicon dioxide layers reaching down through the stack to be bottom of the stack. Then perform differential etching of the silicon dioxide layers in the mold. Form undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stacks into the cavity to complete the mold.

Abstract: A sealed electronic circuit module includes a ceramic chip carrier with a top surface, a cover having a mating surface and a seal at the periphery of the carrier between the carrier and the cover. The seal includes a non-metallic soft lower frame, preferably polyimide, atop the carrier at the periphery of the carrier. There is an upper adhesion layer shaped as a matching an upper frame facing downwardly from the cover towards the lower frame. Above the soft lower frame is a lower metal adhesion layer. Between the upper frame and the lower adhesion layer is a solder layer which has been heated to seal the cover to the chip carrier. The soft frame can include a channel through which a metal to metal via-seal is formed by the lower metal adhesion layer and the solder through the channel through the soft layer or there can be a lateral extension of the lower metal adhesion layer to a distal location beyond the periphery of the soft lower frame.

Abstract: A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.