Abstract: A method for forming a longitudinally magnetically biased dual stripe magnetoresistive (DSMR) sensor element comprises forming a first patterned magnetoresistive (MR) layer. Contact the opposite ends of the patterned magnetoresistive (MR) layer with a first pair of stacks defining a track width of the first magnetoresistive (MR) layer, each of the stacks including a first Anti-Ferro-Magnetic (AFM) layer and a first lead layer. Then anneal the device in the presence of a longitudinal external magnetic field. Next, form a second patterned magnetoresistive (MR) layer above the previous structure. Contact the opposite ends of the second patterned magnetoresistive (MR) layer with a second pair of stacks defining a second track width of the second patterned magnetoresistive (MR) layer. Each of the second pair of stacks includes spacer layer composed of a metal, a Ferro-Magnetic (FM) layer, a second Anti-Ferro-Magnetic (AFM) layer and a second lead layer.

Abstract: Variable space charge effects in the imaging portion of a particle beam projection system due to variations in transmitted beam current are compensated with an additional lens appropriately positioned within the imaging system and having a focal length which varies in response to the transmitted beam current.

Abstract: A method of forming an SRAM transistor cell on a doped semiconductor substrate with a halo region in transistors thereof by the steps including well formation, field isolation formation, threshold voltage implant, gate oxidation; deposition of polysilicon and patterning thereof into gate electrode; post etching anneal; N type LDD photolithography and ion implanting NMOS transistor devices; ion implant halo regions in a transistor; P type LDD photolithography and ion implanting PMOS transistor devices; spacer formation; N+ source/drain photolithography and ion implanting; and P+ source/drain photolithography and ion implanting.

Abstract: A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

Abstract: Form a dielectric layer on a surface of a conductive substrate with a trench through the top surface down to the substrate. Form a barrier layer over the dielectric layer including the exposed surface of the conductive substrate and the exposed sidewalls of the dielectric layer. Form a copper conductor over the barrier layer and overfilling the narrow hole in the trench. Etch away material from the surface of the copper conductor by a CMP process lowering the copper leaving a thin layer of copper over the barrier layer above the dielectric layer aside from the hole. Form a copper passivation by combining an element selected from silicon and germanium with copper on the exposed surfaces of the copper surfaces forming an interface in the narrower hole between the copper and the copper compound located below the dielectric top level.

Abstract: A structure with bit lines and capacitors for a semiconductor memory device is formed by the following steps. Form a gate oxide layer on a doped silicon semiconductor substrate. Form gate electrode stacks juxtaposed with conductive plugs over the gate oxide layer, the conductive plugs being separated by a first dielectric material in a direction oriented transversely of the gate electrode stacks. Form a first interpolysilicon layer above the conductive plugs. Form bit-lines in the first interpolysilicon layer above the first dielectric material. Form a capacitor above a plug and between a pair of the bit-lines.

Abstract: A method of manufacture of self-aligned floating gate, flash memory device on a semiconductor substrate includes the following steps. Form a blanket silicon oxide layer over the substrate. Form a blanket floating gate conductor layer over the silicon oxide layer. Pattern the blanket silicon oxide layer, the floating gate conductor layer and the substrate in a patterning process with a single floating gate electrode mask forming floating gate electrodes from the floating gate conductor layer and the silicon oxide layer; and simultaneously form trenches in the substrate adjacent to the floating gate electrode and aligned with the floating gate electrodes thereby patterning the active region in the substrate. Form a blanket dielectric layer on the device filling the trenches and planarized with the top surface of the floating gate electrodes. Form an interconductor dielectric layer over the device including the floating gate electrodes. Form a control gate conductor over the interconductor dielectric layer.

Abstract: A method is provided for forming a plurality of structures with different resistance values in a single polysilicon film as follows. Form a polysilicon layer upon a substrate. Pattern the polysilicon to expose a portion thereof which is to be reduced in thickness. Partially etch through the polysilicon to produce a reduced thickness thereof while leaving the remainder of the polysilicon with the original thickness. Dope the polysilicon layer through the polysilicon with variable doping as a function of the reduced thickness and the original thickness of the polysilicon.

Abstract: A method for operating a plasma processing system comprises the following steps. Produce a plasma in a plasma processing chamber operating upon a selected workpiece. Perform in situ detection of electromagnetic radiation of a certain wavelength generated in the plasma in the plasma processing chamber. Calculate a first intensity difference of the certain wavelength from a set point of intensity. Halt production of the plasma in the plasma processing chamber if the first intensity difference is outside of specifications.

Abstract: A semiconductor manufacturing tool for charged particle lithography systems such as an EBPS comprises a magnetic deflector with a hub comprising a cylinder mounted on flange. The hub has an opening for a particle beam. Grooves on the surface of the flange at the base of the cylinder and slots in the edge of the cylinder support several deflection coil vanes. Each of the vanes is formed of substrate comprising a thin plate which has a left surface and a right surface. Complementary electrical coils are wound as a planar spirals on the left surface and on the right surface of the vanes with a via connection through the plate interconnecting the coils. The series connected, spiral coils are patterned as mirror images so that the magnetic fields from the coils are additive. To accommodate vanes carrying large currents, the plate is quartz and complementary copper conductor spirals are bonded to the sides of the quartz plate.

Abstract: A via is formed between a copper conductor and a second copper conductor in a thin film electronic device with a copper plug interconnecting the copper conductor and the second copper conductor. Form a stop layer over the first copper conductor and a dielectric layer over the stop layer. Pattern the dielectric and etch stop layers by etching a hole therethrough down into a copper conductor leaving an exposed surface of the copper conductor and exposed sidewalls of the dielectric layer and the etch stop layer. Grow a copper germanide (Cu.sub.3 Ge) compound, thin film at the base of the hole on the exposed surface of the copper conductor from exposure to germane GeH.sub.4 gas. Form a barrier layer over the copper germanide (Cu.sub.3 Ge) compound, thin film, the dielectric layer and the first copper conductor. The barrier layer forms a via hole in the hole. Form a second copper conductor including the copper plug over the barrier layer, the copper plug filling the narrow via hole.

Abstract: This method forms structures with different resistance values from a single polysilicon film formed on a substrate. Form a hard masking layer on the polysilicon film. Form a photoresist mask over the hard masking layer. Partially etch the hard masking layer through the photoresist mask to reduce the thickness of the polysilicon while leaving the remainder of the hard masking layer with the original thickness. The thickness is reduced in locations where a low resistance is to be located in the polysilicon film. Then dope the polysilicon layer through the hard masking layer with variable doping as a function of the reduced thickness and the original thickness of the hard masking layer.

Abstract: A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

Abstract: A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.

Abstract: A single integrated-circuit color camera chip is color sensitive by grouping closely-adjoining light-detecting cells in a photodiode array into triplets. Each pixel of the sensor includes both a read transistor and a write transistor. Each cells in the triplet is similar, but each cell is associated with a color filter of a different color, with red, green or blue cells in an R-G-B system. The proximity and small size of the cells in a triplet allows accurate color differentiation each pixel. Color information is adjusted on-chip for color, brightness and contrast before being sent to an external read device or display device. The color filter is a series of passive layers formed on the integrated circuit surface permitting the selective transmission of light or electromagnetic radiation of certain frequency ranges. The filter may be coated onto a semiconductor wafer after the latter has undergone conventional MOS process steps.

Abstract: A method of manufacturing a magnetoresistive head comprises forming a magnetoresistive structure with a magnetoresistive element with a first AFM element. Perform a first annealing step at a high temperature with a high magnetic field. Form the remaining MR structure including second AFM elements. Perform a low magnetic field (H.sub.ann) annealing step following the fabrication of the second AFM elements. Then perform a no externally applied field (H.sub.ann =0) annealing step at a high temperature to increase the H.sub.ex of the second AFM element to full strength, whereby the stability of the first AFM element is enhanced or increases its H.sub.ex if there were a decrease during the low magnetic field annealing step.

Abstract: A method of forming a copper conductor for a thin film electronic device comprises: forming layers over a conductor into a stack of barrier layer superjacent on top of the substrate, a copper layer on top of the barrier layer, and a hard mask layer on top of the copper layer. The forming a mask on top of the hard mask layer and pattern the stack by etching through the layers down to the substrate on the sides of the mask forming the copper layer into a copper conductor line and leaving sidewalls of the copper conductor line exposed. Grow a copper germanide (Cu.sub.3 Ge) compound passivation layer is selectively grown only on the sidewalls of the copper conductor line.

Abstract: This is a method of forming a vertical memory device on a semiconductor substrate. Start by forming an initial mask with a first array of parallel strips, with a first orientation, on the surface of a silicon oxide layer on a substrate. Then form another mask with transverse strips to form gate trench openings between the first array of strips and the transverse strips. Next, etch floating gate trenches in the substrate through the gate trench openings. Dope the walls of the trenches with a threshold implant and remove exposed portions of the mask. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Strip the remainder of the masks. Form a tunnel oxide layer on the trench surfaces and a floating gate electrode in the trench on the tunnel oxide layer. Above the source/drain regions, form source drain conductor lines in the substrate in a parallel array.

Abstract: Form a split gate EEPROM memory device on a doped silicon semiconductor substrate starting with an initial oxide layer and form an undoped first polysilicon layer thereon. Then form a polysilicon oxide hard mask over the undoped first polysilicon layer for use in patterning the initial oxide layer and the undoped first polysilicon layer which are then etched to form a floating gate electrode stack from the undoped first polysilicon layer and the initial oxide layer on the substrate. Then form a tunnel oxide layer and a doped polysilicon and pattern them into control gate electrode stack, with the control gate electrode stack being located in a split-gate configuration with respect to the floating gate electrode stack.

Abstract: A dynamic mask exposure system and method includes a support for a workpiece, a source of a beam of exposure radiation, and a transmissive dynamic mask with orthogonally arranged matrices of actuator lines and binary pixel units which are opaque or transparent as a function of control inputs to the actuator lines, the transmissive dynamic mask having a top surface and a bottom surface. A control system is connected to supply pixel control signals to the actuator lines of the transmissive dynamic mask to form a pattern of transparent regions and opaque regions. The beam is directed down onto the top surface of the mask. A workpiece and/or an image detection element for detecting a pattern of radiation projected thereon is located on the top surface of the support. The beam passes through the transparent regions and projecting a pattern from the mask onto the support where the workpiece or onto the image detection element is to be located.