Patents Represented by Attorney Gray Cary Ware & Freidenrich, LLP
  • Patent number: 6888254
    Abstract: First and second IP cores are formed on one chip. Each of the first and second IP cores has metal layers. In the first IP core, an uppermost layer of the metal layers is thick and is a layer on which a core power source line is formed. In the second IP core, a metal layers equal in level to the uppermost layer in the first IP core becomes an intermediate layer. In the second IP core, thin intermediate layers are formed on this intermediate layer. Thin intermediate layers are layers on which signal lines are formed and have a narrow wiring pitch. In the second IP core, a layer on which a power source line is formed is provided on the thin intermediate layers.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: May 3, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yamaguchi, Muneaki Maeno
  • Patent number: 6884870
    Abstract: The invention provides a fusion protein including a reporter polypeptide, a linker polypeptide comprising a protease cleavage site, and a repressor polypeptide. The repressor polypeptide represses the activity of the reporter polypeptide by conferring a specific localization in a cell that reduces activity of the reporter activity until the cleavage site is cleaved. A method is also provided for identifying a protease that recognizes a specific protease cleavage site. The invention further provides a method of identifying a compound that activates a protease.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: April 26, 2005
    Assignee: California Institute of Technology
    Inventors: Bruce A. Hav, Christine J. Hawkins
  • Patent number: 6885600
    Abstract: A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: April 26, 2005
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Jack Edward Frayer, William John Saiki, Michael Stephen Briner
  • Patent number: 6885901
    Abstract: A server for supporting LSI manufacturing is used within an LSI manufacturing support system including: a communication line, an LSI manufacturing support server connected to that communication line, IP developer terminals, LSI developer terminals, and an IP management storage, IP development schedule storage and project information storage connected to that LSI manufacturing support server.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: April 26, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuo Tomii
  • Patent number: 6883372
    Abstract: This invention concerns gravity gradiometers for airborne surveys for minerals. The gravity gradiometer comprises an inertially stabilized platform, a rotor that is between 0.4 and 1.5 m in diameter mounted in the stabilized platform, and between twelve and seventy two accelerometers arranged in complements of four each on the rotor; and a signal processor operative to: (i) subtract noise calculated from the mass distribution of the aircraft and the inertially stabilised platform, and by the angles of the gimbals of the stabilised platform; (ii) use measures of the accelerations experienced by the gravity gradiometer to estimate the sensitivities of the gravity gradiometer to the acceleration, and use this estimate to correct the gravity gradiometer output; and (iii), use measures of the rotations to which the gravity gradiometer is subjected to calculate the contribution of rotation to the gravity gradiometer noise, and to remove the contribution of rotation to said gravity gradiometer noise.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: April 26, 2005
    Assignee: BHP Billiton Innovation Pty Ltd
    Inventors: Edwin Hans van Leeuwen, Ken G. McCracken, James Beresford Lee, Robert John Turner
  • Patent number: 6878562
    Abstract: A process for shifting the bandgap energy of a quantum well layer (e.g., a III-V semiconductor quantum well layer) without inducing complex crystal defects or generating significant free carriers. The process includes introducing ions (e.g., deep-level ion species) into a quantum well structure at an elevated temperature, for example, in the range of from about 200° C. to about 700° C. The quantum well structure that has had ions introduced therein includes an upper barrier layer, a lower barrier layer and a quantum well layer. The quantum well layer is disposed between the upper barrier layer and the lower barrier layer. The quantum well structure is then thermally annealed, thereby inducing quantum well intermixing (QWI) in the quantum well structure and shifting the bandgap energy of the quantum well layer. Also, a photonic device assembly that includes a plurality of operably coupled photonic devices monolithically integrated on a single substrate using the process described above.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: April 12, 2005
    Assignee: Phosistor Technologies, Incorporated
    Inventors: Boon-Siew Ooi, Seng-Tiong Ho
  • Patent number: 6878567
    Abstract: A method and apparatus for fabrication of passivated microfluidic structures is disclosed. The method includes providing a substrate having a microfluidic structure formed therein. The microfluidic structure is embedded by an embedding layer. The method further includes passivating the embedded microfluidic structure by locally heating the microfluidic structure surface in a reactive atmosphere, wherein the passivated microfluidic structure is suitable for transporting a fluid.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: April 12, 2005
    Assignee: Intel Corporation
    Inventors: Paul Winer, George P. Vakanas
  • Patent number: 6872574
    Abstract: The present invention provides methods for analyzing proteomes, as cells or lysates. The analysis is based on the use of probes that have specificity to the active form of proteins, particularly enzymes and receptors. The probes can be identified in different ways. In accordance with the present invention, a method is provided for generating and screening compound libraries that are used for the identification of lead molecules, and for the parallel identification of their biological targets. By appending specific functionalities and/or groups to one or more binding moieties, the reactive functionalities gain binding affinity and specificity for particular proteins and classes of proteins. Such libraries of candidate compounds, referred to herein as activity-based probes, or ABPs, are used to screen for one or more desired biological activities or target proteins.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: March 29, 2005
    Assignee: The Scripps Research Institute
    Inventors: Benjamin F. Cravatt, Erik Sorensen, Matthew P. Patricelli, Martha Lovato, Gregory Adam
  • Patent number: 6872533
    Abstract: The present invention provides methods for determining cancer susceptibility in a human subject by identifying in a nucleic acid sample from the subject, a nucleotide occurrence of a single nucleotide polymorphism (SNP) of the STK15 gene, including the STK15 Ile31 polymorphism. The invention provides isolated polynucleotides, polypeptides, specific binding pair members, and cells useful for identifying agents that affect tumor susceptibility. Furthermore, the invention provides methods for detecting low penetrance tumor susceptibility genes.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: March 29, 2005
    Assignee: The Regents of the University of California
    Inventors: Amanda E. Toland, Allan Balmain
  • Patent number: 6870233
    Abstract: A multi-bit Read Only Memory (ROM) cell has a semiconductor substrate of a first conductivity type with a first concentration. A first and second regions of a second conductivity type spaced apart from one another are in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. The ROM cell has one of a plurality of N possible states, where N is greater than 2. The possible states of the ROM cell are determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: March 22, 2005
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Bomy Chen, Kai Man Yue, Andrew Chen
  • Patent number: 6868015
    Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates are formed in each of the active regions by forming a conductive layer of material. Trenches are formed in the row direction across the active regions, and are filled with a conductive material to form blocks of conductive material that are the control gates. Sidewall spacers of conductive material are formed along the floating gate blocks to give the floating gates protruding portions that extend over the floating gate.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: March 15, 2005
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Chih Hsin Wang
  • Patent number: 6868293
    Abstract: A system and method are disclosed for performing energy usage management within a network. The system may include an energy management system, such as a thermostat device, that may be associated with an energy consuming entity, such as a residence. A server may be remotely located from the energy consuming entity and may perform one or more energy curtailment management operations within the network. The server may be in communication with the energy management system over the network. One or more software applications may be stored thereon for remotely controlling the energy management system in accordance with a particular energy curtailment management operation. Additionally, a database may be associated with the server for storing curtailment event information relating to the network. A signal may be transmitted by the server to the thermostat device to alter an offset temperature setting of the thermostat device thereby remotely controlling the operation of the thermostat device.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: March 15, 2005
    Assignee: Itron, Inc.
    Inventors: Allan J. Schurr, Gaymond Yee
  • Patent number: 6867045
    Abstract: The present invention provides an in vitro method useful for the diagnosis of a thrombotic disorder in a subject, having or at risk of having the disorder. Specifically, the disorder exemplified herein is associated with APC resistant Factor V and Va. The clotting time of a test sample is analyzed in the presence and absence of APC and compared with a standard reference sample in order to diagnose the subject.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: March 15, 2005
    Assignees: The Scripps Research Institute, The Regents of the University of California
    Inventors: John H. Griffin, Samuel I. Rapaport, Dzung T. Le
  • Patent number: 6863888
    Abstract: An isolated polypeptide (JNK) characterized by having a molecular weight of 46 kD as determined by reducing SDS-PAGE, having serine and threonine kinase activity, phosphorylating the c-Jun N-terminal activation domain and polynucleotide sequences and method of detection of JNK are provided herein. JNK phosphorylates c-Jun N-terminal activation domain which affects gene expression from AP-1 sites.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: March 8, 2005
    Assignee: The Regents of the University of California
    Inventors: Michael Karin, Masahiko Hibi, Anning Lin, Roger Davis, Benoit Derijard
  • Patent number: 6861698
    Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction, and an apparatus formed thereby. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that are filled with a conducting material such as metal or metalized polysilicon to form blocks of the conducting material that constitute source lines. Each source line extends over and is electrically connected to one of the source regions in each of the active regions.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: March 1, 2005
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Chih Hsin Wang
  • Patent number: 6858208
    Abstract: A transgenic non-human animal of the species selected from the group consisting of avian, bovine, ovine and porcine having a transgene which results in disrupting the production of and/or activity of growth differentiation factor-8 (GDF-8) chromosomally integrated into the germ cells of the animal is disclosed. Also disclosed are methods for making such animals, and methods of treating animals with antibodies or antisense directed to GDF-8. The animals so treated are characterized by increased muscle tissue.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: February 22, 2005
    Assignee: The Johns Hopkins University School of Medicine
    Inventors: Se-Jin Lee, Alexandra C. McPherron
  • Patent number: 6859838
    Abstract: An internet-based personalizable broadcast network for viewing information in the form of streaming audio and/or video. The network includes an input for receiving streaming media content, organized into a plurality of news channels. The network includes some type of media server for playing the received streaming media content as a presentation to a user. The network further includes storage for an array of cursors. At least some of the plurality of news channels have at least one associated cursor in the array of cursors and an associated cursor indicates where, in the news channel associated with that associated cursor, the presentation of the news channel stopped. Logic is provided for updating the array of cursors as news channels are provided to the user thereby allowing the user to limit repetition of news channels, or portions of news channels, already presented to the user.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: February 22, 2005
    Assignee: ON24, Inc.
    Inventors: Rajiv Puranik, Hemant Gokhale, James Lenigk
  • Patent number: 6855980
    Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction, and an apparatus formed thereby. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indentations or different widths. The trenches are filled with a conducting material to form blocks of the conducting material that constitute source regions with a first portion that is disposed adjacent to but insulated from the floating gate, and a second portion that this disposed over but insulated from the floating gate.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: February 15, 2005
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Chih Hsin Wang, Amitay Levi
  • Patent number: 6852492
    Abstract: The methods, compositions and apparatus disclosed herein are of use for nucleic acid sequence determination. The methods involve isolation of one or more nucleic acid template molecules and polymerization of a nascent complementary strand of nucleic acid, using a DNA or RNA polymerase or similar synthetic reagent. As the nascent strand is extended one nucleotide at a time, the disappearance of nucleotide precursors from solution is monitored by Raman spectroscopy or FRET. The nucleic acid sequence of the nascent strand, and the complementary sequence of the template strand, may be determined by tracking the order of incorporation of nucleotide precursors during the polymerization reaction. Certain embodiments concern apparatus comprising a reaction chamber and detection unit, of use in practicing the claimed methods. The methods, compositions and apparatus are of use in sequencing very long nucleic acid templates in a single sequencing reaction.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: February 8, 2005
    Assignee: Intel Corporation
    Inventors: Andrew Berlin, Steven J. Kirch, Gabi Neubauer, Valluri Rao, Mineo Yamakawa
  • Patent number: 6853584
    Abstract: A non-volatile memory semiconductor device has a circuit to compensate for the variation in the data pattern to be programmed. The variation in the data patter creates a variation in the current requirement. The array receives a plurality of data pattern signals which affect the total amount of current flowing into a plurality of columns and into the memory array. A high voltage source generates an output which is supplied along a conducting path connected to the group of columns. A pass transistor is in the conducting path controlling the current flow in the conducting path. A current source has a first terminal and a second terminal with the first terminal connected to the output of the high voltage generator and the second terminal connected to the gate of the pass transistor. A plurality of current sources are collectively connected to a node.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: February 8, 2005
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hung Q. Nguyen, Sang Thanh Nguyen, Elbert Lin, Anh Ly