Abstract: A system and method provides signaling privacy for communications between nodes of a communications network (30). Multiple logical links exist between distinct network nodes (38-40, 42, 50-53) of the communication network (30). Signaling privacy is achieved by a subscriber unit (80) providing encryption/decryption of signaling data messages at the messaging level. The subscriber unit (80) employs a signaling encryptor/decryptor (86) along the signaling path, which enables the signaling data messages to be separately encrypted from data on the traffic channel. The encrypted signaling data can then be sent along a different logical link from the traffic, while maintaining cipher key synchronization between the signaling encryptor/decryptor (86) and a network encryptor/decryptor (78) at a remote end of the logical link which transports the encrypted signaling data.

Abstract: A programmable cryptographic system (100) provides high performance cryptographic processing support for cryptographic algorithms. Two or more independent cryptographic algorithms may be performed at the same time through the processes of background staging and algorithm multi-tasking. A four stage software instruction pipeline and dynamically programmable function units support high performance cryptographic processing performance on the order of 60 mega bits per second (Mbps) aggregate throughput.

Abstract: A cryptographic controller (100) installs and manages a channel for processing data units. The cryptographic controller (100) performs background staging of programs, context, and data units for the programmable crypto engine (14) and configurable crypto engine (16). The cryptographic controller (100) is a secure, hardware operating system capable of managing high performance crypto processing on the order of 1500 million instructions per second (MIPS).

Abstract: A method for assigning a system location to an ISU (32) residing in a wireless communication system coverage area (20) that has a plurality of billing territories (40). Base points (42) are defined to be proximate the billing territories (40) such that each of the base points (42) provides a system location for a corresponding billing territory (40). Each of the billing territories (40) has a plurality of reference points (44) distributed therein in accordance with a geographic independent algorithm such that each of the reference points (44) is described by an offset from the corresponding base point (42) of the corresponding billing territory (40). By obtaining an actual location (54) of the ISU (32) and identifying one of the reference points (44) closest to the actual location (54), the ISU (32) is assigned the system location of the identified reference point (44). In a preferred embodiment, the method and apparatus of the present invention are used in a mobile satellite system (19).

Abstract: In a global satellite communication system (10) that provides antenna beams that move with respect to Earth's surface, gateways (22) send ring alerts directed to subscriber units (26) based on a list of antenna beams. The list of antenna beams is determined by a dot product between a subscriber unit's basis vector and antenna beam vectors. Ring alerts are transmitted in antenna beams when the dot product exceeds a predetermined threshold. Subscriber units listen for ring alerts in the same antenna beams of the list by calculating the list the same way the gateway calculates the list.

Abstract: A multichannel time shared demodulator (10) is implemented in an efficient ASIC architecture that provides routing-of user voice channels and access channels to a collection of time-shared processors for rapid signal detection, tracking and demodulation. The channels are routed in a random order and then processed by a time-shared symbol synchronization processor (18) for voice channels and a time-shared detection processor for access channels. The signals are over-sampled via a time-shared interpolation filter. The interpolation process yields a ten to one over sampling ration of all signals. A synchronized clock is used to choose the phases of the interpolation filter outputs.

Abstract: A mouse system (100) for authenticating a user and providing access to a computer (212) includes a pointing device and card reader (106) which share a computer interface port (222) of the computer (212). User information is read off the card (104), converted to pointing device codes, and provided to the computer (212). The computer reconverts the pointing device codes to user information to deny or grant access. The card reader (106) is capable of reading commercially available smart cards, credit cards, and other media having user information electronically stored on the card (104).

Abstract: A software programmable radio (200) receives information to configure a reconfigurable resource (208) to perform an operation based on the information. A processor (210) within the reconfigurable resource performs a software program in accordance with the operation, such as a waveform for communicating via a spread spectrum technique. The method includes the steps of checking (304) for a valid license granted to the radio to determine when the radio is authorized for use in the network. A controller (204) configures the radio to perform the operation based on the information.

Abstract: In a satellite communication system, beamforming is performed at baseband frequencies forming only beams which convey information. A received signal is applied to a downconverter (FIG. 1, 30), followed by a channelizer (50), and digital beamformer (60). The order of operations being reversed in order to generate a transmit beam. By performing the beamforming at baseband, the system can be allowed to form only those beams which convey information between a communications node and a subscriber. As a result, the system provides communication services to subscribers in a more cost-effective manner.

Abstract: A space-based communication system (30), includes a transmission terminal having a transmission antenna (42) and a power amplifier (40) to power the transmission antenna, the power amplifier to generate a power output sufficient to generate an RF signal through the transmission antenna (42), a receive terminal including a receive antenna (45) to receive the RF signal from the transmission terminal and a low noise amplifier (43) to amplify the RF signal channeled through the receive antenna, and a thermoelectric cooler (62) for cooling the low noise amplifier (43) to a predetermined temperature for increasing the sensitivity of the low noise amplifier to minimize the power output generated by the power amplifier required to generate the RF signal thereby minimizing the overall power requirements of the spaced-based communication system (30).

Abstract: Cellular communication systems (20) use repeaters (50) to communicate with subscriber units (24) otherwise shadowed from base stations (22). A networked repeater (50) is provided for use in a cellular communication system with low-earth orbit satellites (22) and mobile subscriber units (24). Networked repeater (50) includes a base transceiver module (54) for communicating with the base stations (22) and a plurality of subscriber transceiver modules (56), each of which communicates with subscriber units (24). The base transceiver module (54) is located so as to be unshadowed, i.e. able to have unimpeded communication with at least one of the satellites (22). The subscriber transceiver module (56) is located so as to provide unshadowed communication with the subscriber units (24) that would otherwise be shadowed, i.e. unable to have unimpeded communication with any of the satellites (22).

Abstract: An amplifier system (100) for transmitting wideband multicarrier communication signals in a satellite communication system uses wideband envelope elimination and restoration amplifiers (200). The system upconverts channelized IF signals to provide a wideband multicarrier RF output signal between 20 and 30 GHz having a bandwidth between 100 and 200 MHz.

Abstract: A processing system includes a control flow monitor (CFM) checker for verifying a sequence of instructions performed by a pipelined processor (101). The CFM checker provides fail safe assurance against run-time errors in the sequence of instructions performed by a processor. The CFM checker verifies instruction sequence during run-time within 32 instruction cycles. The processing system provides an improved system and method having a CFM checker which minimizes wasted instruction cycles when performing branch instructions in a software program. Using a prefetch capability of an instruction pipeline and storing fixwords sequentially in memory, eliminates unnecessary instructions to fetch fixword values from external tables, thereby saving instructions and instruction cycles.

Abstract: A communication apparatus (100) provides an interface between a cellular encryption and decryption apparatus (150) and a telephone line (91) allowing for communication of secure data of the telephone line using a regular telephone (70). The communication apparatus (100) provides for the receipt of incoming secure data in an unattended data mode, and also allows the telephone to be used in either a secure mode or clear mode. The communication apparatus monitors the telephone line (91) for secure tones while operating in the clear mode. When a secure tone is detected, the communication apparatus (100) breaks the path between the PSTN (90) and the telephone (70) and routes the signals to the cellular encryption and decryption apparatus (150) to establish a secure call.

Abstract: A low power serial A/D converter cascades multiple stages (20) of a novel track-and-hold circuit (22) to implement a pipelined A/D converter. The track-and-hold circuit (22) is implemented using a differential structure to cancel out signal droop. This allows extremely high tracking bandwidths to be achieved while maintaining long hold times. Each stage (20) of the pipeline includes a binary quantizing circuit (24) which performs a 1-bit binary estimate of the data and a summing circuit (26) which updates the output of its track-and-hold circuit (22) to allow the next bits to be decided by the following stages.

Abstract: Classifiers (110) and a selector (112) perform an identification method (300) to identify an ordered set of vectors (e.g., spoken commands, phoneme identification, radio signatures, communication channels, etc.) representing a class as one of a predetermined set of classes. Training processor (104) performs a training method (200) to train a set of models and store the models in a model memory (108). Classifiers (110) receive models from the model memory and combine the models with the ordered set of vectors to determine a set of scores. The selector associates the set of scores with the predetermined set of classes to identify the ordered set of vectors as a class from the predetermined set of classes.

Abstract: A structure (24) includes a plurality of repeaters (34), each having a primary transceiver (36) and a secondary transceiver (38) electromagnetically located upon a clear side (30) and a blocked side (32), respectively, of a barrier (26). Each primary transceiver (36) and secondary transceiver (38) communicate using an intra-repeater signal (46). Each intra-repeater signal (46) is output from its respective primary transceiver (36), combined with other intra-repeater signals (46) by a combiner (50), passed over a communication infrastructure (22), separated from other intra-repeater signals (46) by a separator (54), and input to its respective secondary transceiver (38). Optionally, each intra-repeater signal (46) may be retrieved from the communication infrastructure (22), separated from other intra-repeater signals (46) by a separator (62), amplified by a bandpass amplifier (64), combined with other intra-repeater signals (46) by a combiner (66), and inserted back into the communication infrastructure (22).

Abstract: A configurable cryptographic processing engine (100) provides high performance cryptographic processing support for symmetric combiner type cryptographic algorithms. As many as two independent cryptographic algorithms may be performed at the same time through the processes of background staging and algorithm multi-tasking. A 3-stage instruction pipeline, dynamically configurable cryptographic co-processor (550), and 32-bit RISC based architecture support high performance cryptographic processing performance on the order of 60 Mbps aggregate throughput.

Abstract: A sequence-controlled digital circuit (21) is presented. The circuit (21) includes a divider (55) and a plurality of transparent latches (51-54) which together form a latch-based sequencer (42). Typically, a clock signal (43) is divided by the divider (55) into an inverted half-clock signal (45) and a non-inverted half-clock signal (44), each enabling alternate latches (51-54) arranged in a cascade. In the cascade, an output of each latch (51-54) drives an input of the following latch (51-54), one such being an inverting output and the rest non-inverting outputs, to form a twisted-loop counter (50). Each output of each latch (51-54) drives a clock input of a flip-flop (61-68), with a serial input signal (46) driving all data inputs, to form a temporal-to-spacial converter (40). Only the divider (55) operates at the rate of the clock signal (43).

Abstract: A radio-frequency circuit (20) includes a hybrid integrated circuit (24) having a passive circuit element (38) and a d-c biasing circuit element (54) embedded within a first substrate (32) of a low cost and rugged first semiconducting material, and first and second active circuit elements (36, 40) embedded within second and third substrates (44, 46), respectively, of a second semiconductor material having the characterisitics of greater frangibility but higher gain than the first semiconductor material. The first and second activ circuit elements (36, 40) are substantially first and second single components (36, 40), and are each electrically coupled to the passive circuit element (38). The d-c biasing circuit element (54) is electrically coupled to the first and second active circuit elements (36, 40). The second and third substrates (44, 46) are physically coupled to the first substrate (32), which is thicker than either the second or third substrate (44, 46).