Abstract: A system and method for a user interface to input URL address data obtained from captured video frames while simultaneously viewing a television broadcast, the system having a television with associated television screen, a set-top box, and a remote control. The invention also includes means for initiating a video-viewing mode (where the television receives a television signal via the set-top box and displays the television signal on the television screen), a capture manager for capturing image data frames from the television signal, an interface manager for displaying information windows on the display screen, and a search manager for retrieving data pages from a networked source such as the Internet.

Abstract: A system and method to manipulate information in an audio decoder, the system having a demultiplexer to separate the information into packets of audio data and packet parameters, a control manager for controlling the packet parameters, and an audio decoder to manipulate the packets of audio data in response to the packet parameters. The invention also includes a control processor for passing host parameters to the control manager and a digital-to-analog converter to convert the audio information from a digital signal to an analog signal.

Abstract: A system comprises a refined psycho-acoustic modeler for efficient perceptive encoding compression of digital audio. Perceptive encoding uses experimentally derived knowledge of human hearing to compress audio by deleting data corresponding to sounds which will not be perceived by the human ear. A psycho-acoustic modeler produces masking information that is used in the perceptive encoding system to specify which amplitudes and frequencies may be safely ignored without compromising sound fidelity. The present invention includes a system and method for efficiently implementing a masking function in a psycho-acoustic modeler in digital audio perceptive encoding. In the preferred embodiment, the present invention comprises a non-logarithmically based representation of individual masking functions utilizing minimally-sized look-up tables.

Abstract: A system and method for efficiently designing integrated circuits provides a verification manager for verifying an integrated circuit design, a synthesis manager for synthesizing the integrated circuit design, a backend manager for implementing the integrated circuit design, and a processor for simultaneously controlling the verification manager, the synthesis manager, and the backend manager to create the integrated circuit design. The system and method generates a series of regression checkpoints controlled by the verification manager, and a series of timing checkpoints controlled by the synthesis manager to facilitate and expedite the integrated circuit design procedure.

Abstract: A method for reducing noise distortions in a speech recognition system comprises a feature extractor that includes a noise-suppressor, one or more time cosine transforms, and a normalizer. The noise-suppressor preferably performs a spectral subtraction process early in the feature extraction procedure. The time cosine transforms preferably operate in a centered-mode to each perform a transformation in the time domain. The normalizer calculates and utilizes normalization values to generate normalized features for speech recognition. The calculated normalization values preferably include mean values, left variances and right variances.

Abstract: A system and method for multi-level context switching in an electronic network comprises a control state machine configured to implement a data priority scheme, a return address generator configured to hold and release return addresses for interrupted instruction modules in accordance with the data priority scheme and context information from the electronic network, and a processor configured to process data from the electronic network in accordance with the data priority scheme and the context information. Receive registers stores data received from the electronic network. The control state machine includes a switch address generator and a program counter select. The switch address generator outputs a switch address, which is an address for a first instruction for a selected-context instruction module. The return address generator holds and releases the return addresses, which are addresses of next consecutive instructions, when an instruction module is interrupted for a context switch.