Abstract: A shared memory system (10) is provided which interfaces with a shared memory bus (14). The shared memory bus (14) interfaces with a plurality of peripherals (12) through memory interfaces (16). Each of the memory interfaces (16) is operable to receive addresses from the associated one of the peripheral units (12) and communicate with the shared memory system (10) to process the addresses and subsequent data transfers in an ordered manner. The shared memory system (10) has associated therewith an arbitration logic circuit (78) that is operable to service bus requests from each of the memory interfaces (16). When a bus request is received, the requesting one of the memory interfaces (16) is allowed to access a single byte of data, after which it relinquishes the bus to another one of the memory interfaces (16).

Abstract: A ballistic weapon is disclosed having a barrel with a forward end to which a barrel extender is secured. The barrel extender includes a cylindrical outer body portion, a forward ring-like portion and a rearward wall portion, which together define a forward chamber in communication with the bore of the barrel of the weapon. A plurality of apertures extend through the rearward wall portion and are angularly spaced equidistances apart around a central longitudinal axis of the bore of the barrel. The apertures define central axes which are substantially parallel to the central longitudinal axis of the bore of the barrel. The apertures connect the forward chamber to an interior annular space extending between the exterior of the barrel and a perforated shroud extending exteriorly around the barrel.

Abstract: An output driver is provided for operating in a primary power supply environment to drive an output system that can have voltages associated therewith that are higher than the primary power supply level. The driver includes a pull-down N-channel (34) and a pull-up P-channel transistor (44). An output node (40) is driven by the transistor (34) and (44). An N-channel protection device (38) is disposed between node (40) and transistor (34) and an N-channel transistor (48) is disposed between node (40) and transistor (44). Transistor (38) has the gate thereof biased to the primary supply voltage level and the transistor (48) has the gate thereof biased to a voltage slightly above the primary supply voltage level.

Abstract: A very high gain cascode amplifier includes a cascoded differential structure wherein a cascoded N-channel leg comprised of two series connected transistors (56) and (58) are connected between an output node (30) and ground with a corresponding P-channel cascode leg comprised of series connected P-channel transistors (38) and (40) connected between node (30) and V.sub.DD. Transistor (58) is connected to bias voltage, with transistor (56) having a gate thereof connected to a bias circuit (72) which provides gain thereto to increase the gain of a cascoded leg while not introducing any error into the amplifier. The bias circuit (72) has an imbedded structure that sets the gate voltage of transistor (56) to a voltage equal to one threshold voltage plus twice the V.sub.on voltage of transistors (56) and (58).

Abstract: The present invention disclosed and claimed herein comprises a backup power system to supply current to an electromechanical actuator (50) to position a mechanical device (52) to a fail-safe position upon failure of a primary electric power source (12). A capacitor (40) is provided for storing energy. The capacitor (40) is charged by the primary electric power source (12). A relay device (35) is also provided for disconnecting the primary control signal upon failure of the primary electric power source (12) and connecting the capacitor (40) to the electromechanical actuator (50) to supply electric current to the electromechanical actuator (50) to position the mechanical device (52) to a fail-safe position. The relay device (35) comprises a transistor (32) which is kept turned off by the primary electric power source (12) and upon failure of the primary electric power source (12), turns on and energizes an electric relay coil (34).

Abstract: A mapping system is provided for mapping a first contone image and a second bi-level higher resolution image to an output image space for an electrophotographic marking engine, utilized as a printer. A bi-modal hardware device (22) is provided for receiving the information for the two images and then mapping it to the output image space in the marking engine (10). The pixel data associated with the high resolution image is stored in a FIFO (164) and then count values stored in a FIFO (158) associated with the portion of the line in the output image space that is associated with the high resolution image. The pixel data for the portion of the line associated with the low resolution image is stored in a FIFO (182) with a corresponding count value stored in a FIFO (178). A counter is then operable to determine how many pixels of the high resolution image are to be mapped in the output image space.

Abstract: A reconfigurable integrated circuit chip includes an output terminal (42) which is connected to the output of an inverting amplifier (44). The integrated circuit chip (10) includes an output terminal (46) which is connected to one input of a comparator (22). The other end of comparator (22) is connected to an internal voltage reference device (48). The output of comparator (22) is connected to the input of the inverting amplifier (44). The integrated circuit chip (10) may be configured as a linear regulator when a transconductance device (14) is connected between a DC power supply (12) and a load and an integrator (24) is connected between terminal (42) and the control input of the transconductance device (14). The integrated circuit chip (10) is configured as a switching regulator when a gated switch (14) is connected between a DC power supply (12) and a switching node (65) wherein the gated switch (14) is gated by the signal output by the output terminal (42).

Abstract: A preprocessing system for preprocessing input data to a neural network includes a training system for training a model (20) on data from a data file (10). The data is first preprocessed in a preprocessor (12) to fill in bad or missing data and merge all the time values on a common time scale. The preprocess operation utilizes preprocessing algorithms and time merging algorithms which are stored in a storage area (14). The output of the preprocessor (12) is then delayed in a delay block (16) in accordance with delay settings in storage area (18). These delayed outputs are then utilized to train the model (20), the model parameter is then stored in a storage area (22) during run time, a distributed control system (24) outputs the data to a preprocess block (34) and then preprocesses data in accordance with the algorithms in storage area (14). These outputs are then delayed in accordance with a delay block (36) with the delay settings (18).

Abstract: A personal data unit (PDU) is operable to collect video information via a camera (12) and audio information via a microphone (14). The PDU (10) utilizes a cellular link for transmission of the collected information to a central station (27). Position/time information is received from a GPS satellite network (22) via an antenna (24). This allows the system to be packaged such that it can be attached to an individual and carried with that individual.

Abstract: An analog modulator is provided having seven switched-capacitor integrators (62)-(74) disposed in a leap-frog filter configuration with a plurality of feedback taps (76)-(88) provided from the output to each of the integrators (62)-(74). These are summed in a summation junction (90), the output thereof input to a quantizing circuit (92) for input back to a summation junction alter a D to A circuit (60) for summation with the analog input signal and then input to the first integrator (62). The first feedback structures (98)-(102) are provided for connection between the output of the last of the integrated structures (74) and the input of the preceding one thereof such that the feedback structure (98) is connected across integrators (64) and integrator (66), feedback structure (100) connected between integrators (68)-(70) and integrator (102) connected against integrators (72) and (74).

Abstract: A delta-sigma analog/digital converter is provided for operating in the analog domain to generate a digital value that is to be processed by a digital signal processor (DSP) (26) to provide on the output a digital output. Each data node in each processing element in the DSP (26) is mirrored by the way of a corresponding data node in the mirror circuit (36). This results in the addition of noise via a noise adder (28) such that each data node in the main portion of the DSP (26) that can draw current from the power supply during a transition will have a corresponding complement node in the mirror circuit (36). Each data node in the mirror circuit will add noise via a transition drawing current from the power supply whenever the transition does not occur at the corresponding data node in the main portion of the DSP (26). Therefore, di/dt noise will be added for each cycle, regardless of the data pattern.

Abstract: A shutter control mechanism for 3-D glasses includes a control circuit (28) associated with the glasses, the glasses having 3-D lenses (20) and (22). The control circuitry (28) receives commands from a control transmitter (16) in the form of synchronization pulses and command signals. The command signals are operable to vary the operating parameters of the lenses (20) and (22). Specifically, the duty cycle of the left lens (22) and the right lens (20) are varied such that they can either be at a fifty percent duty cycle, greater than a fifty percent duty cycle or less than a fifty percent duty cycle, wherein the amount of time that each of the lenses is on can be controlled for a given frame length.

Abstract: A battery charge controller (50) is provided which includes a PWM switch controller (36) that is operable to control a switching regulator to supply current to a battery (10) in either a current regulation mode or a voltage regulation mode. A charge control (40) is operable to control the charging operation such that multiple modes of operation are selectable by an external programmable pin. The three modes provided are: a constant voltage mode, a dual-current mode and a pulse-current mode. The constant voltage mode provides for a conditioning state followed by a bulk charging state followed by a maintenance state. In the bulk charging state, current regulation is provided at a maximum current until a charged condition occurs, at which time the charger is placed in a voltage regulation mode.

Abstract: A cartridge is disclosed for use in a ballistic weapon system. The cartridge includes a tubular case and a ballistic projectile. The projectile has an annular groove which extends into an exterior periphery of the projectile. The tubular case has a cylindrical sidewall and a substantially closed rearward end. The cylindrical sidewall defines an interior cavity for receiving at least a rearward portion of the projectile. An annular lug is integrally formed with the cylindrical sidewall and inwardly extends from the sidewall into the annular groove of the projectile, interlocking the projectile and the tubular case. Longitudinal slits are formed in the forward end of the tubular case to allow the case to expand for receipt of the projectile until the annular lug is aligned with and then inserted into the annular groove of the projectile.

Abstract: An adhesive composition is comprised of a mixture of an EVA copolymer and two tackifying resins, a high temperature tackifying resin and a low temperature tackifying resin. The viscosity of the adhesive composition is between 2,000 cps to 80,000 cps over a temperature range of 250.degree. F. to 380.degree. F. The composition comprises 60% by weight of the copolymer, 15% by weight of the low temperature tackifying resin and 25% by weight of the high temperature tackifying resin.

Abstract: A ventilated shoe for ventilating the foot is disclosed. The ventilated shoe contains an outer sole (14). A heel pad (16) is disposed at the rear end of the outer sole (14). An intake manifold (26) is disposed near the front of the outer sole (14). The intake manifold (26) is connected to pump cells (20), (22) and (24). An exhaust manifold (46) is also connected to pump cells (20), (22) and (24). The intake manifold (26) only allows air to flow through the manifold (26) into the pump cells (20), (22) and (24). The exhaust manifold (46) only allows air to flow out of the manifold (46) from the pump cells (20), (22) and (24). The pump cells (20), (22) and (24) are filled with an open-celled foam (70) so that when no pressure is being applied to the pump cells (20), (22) and (24), they draw air in through the intake manifold (26). When pressure is applied to the pump cells (20), (22) and (24), the open-celled foam (70) is compressed and the air is expelled through the exhaust manifold (46).

Abstract: A method for changing the frequency of a low-pass Finite Impulse Response (FIR) filter with a fixed frequency clock utilizes a decimation-by-coefficient technique. The decimation-by-coefficient method utilizes a single set of coefficients that are stored in a coefficient Read Only Memory (ROM) (64). Data is input to an elastic buffer (60) with multiplications performed by a multiplication circuit (62). To realize a low frequency filter, all coefficients are utilized in the multiplication operations with sequential multiplies. These are accumulated in register (70), this providing a high precision filter. To increase frequency by a factor of two--to decimate the coefficients by a factor of two, it is only necessary to utilize every other coefficient, such that only a single fixed clock (78) is required.