Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.

Abstract: Methods and apparatuses provide voltage regulation for a processor. Control or configuration parameters for a voltage regulator (VR) are provided digitally over a configuration bus to a VR controller. The parameters may be provided directly from a storage element, or via a processing element or processor core. Based in whole or in part on the parameters, the VR controller provides an output control signal to affect a power output from a power converter to the processing element. In one embodiment, the VR controller is integrated onto the same IC as the processing element.

Abstract: In some embodiments, a chip comprises control circuitry to provide inband signals, inband output ports, and transmitters to transmit the inband signals to the inband output ports. The control circuitry selectively includes loopback initiating commands in the inband signals. Other embodiments are described and claimed.

Abstract: A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Abstract: Machine-readable media, methods, and apparatus are described to recover from stream under-run and/or over-run conditions. In some embodiments, an audio controller may discard any partial sample block of the stream.

Abstract: According to embodiments of the subject matter disclosed in this application, the age of a target circuit component in a semiconductor device may be monitored by using at least one aging leakage oscillator and a reference leakage oscillator. An aging leakage oscillator is stressed whenever the target circuit component is used while a reference oscillator is not. Due to aging effects on the aging leakage oscillator, the frequency ratio between the aging and the reference leakage oscillators changes over time. Such a frequency ratio change over time may be used to determine the age of the target circuit component. Compared to CMOS based aging oscillators, the frequency ratio between an aging and a reference leakage oscillators changes more significantly over time.

Abstract: Embodiments are generally direct to a method and apparatus for generating a header in a communication network. In one embodiment, receiving at a node on a first communication link a protocol data unit (PDU), generating a header that is non-specific to a particular communication protocol associated with the PDU when received at the node, the header to facilitate encapsulation and transportation of the PDU through a second communication link to deliver the PDU to a memory-based service interface of another node on the second communication link.

Abstract: According to embodiments of the disclosed subject matter in this application, a power management system with multiple voltage regulator (“VRs”) may be used to supply power to cores in a many-core processor. Each VR may supply power to a core or a part of a core. Different VRs may provide multiple voltages to a core/part in the many-core processor. The value of the output voltage of a VR may be modulated under the direction of the core/part to which the voltage regulator supplies power. In one embodiment, the multiple VRs may be integrated with cores in a single die. In another embodiment, the power management system with multiple VRs may be on a die (“the VR die”) separate from the die of the many-core processor. The VR die may be included in the same package as the many-core processor die.

Abstract: An arrangement is provided for performing Montgomery multiplications. A Montgomery multiplication comprises a plurality of iterations of basic operations (e.g., carry-save additions), and is performed by a Montgomery multiplication engine (MME). Basic operations in each iteration may be performed by multiple Montgomery multiplication processing elements (MMPEs). An MME may be arranged to pipeline the process of performing iterations of multiple basic operations and other operations required to complete a Montgomery multiplication both horizontally and vertically. An MME may also be arranged to interleave processes of performing two Montgomery multiplications.

Abstract: A backplane employed in a switch fabric, having the capability to allow signal communication between at least two modules. Two or more of the modules being adapted to employ different topologies from the following types of topologies: star, dual star, mesh, and cascaded mesh.

Abstract: A system and method for the design and operation of a cache system with differing cache location lengths in level one caches is disclosed. In one embodiment, each level one cache may include groups of cache locations of differing length, capable of holding portions of a level two cache line. A state tree may be created from data in a sharing vector. When a request arrives from a level one cache, the level two cache may examine the nodes of the state tree to determine whether the node of the state tree corresponding to the incoming request is already active. The results of this determination may be used to inhibit or permit the concurrent processing of the request.

Abstract: An arrangement is provided for performing the KASUMI ciphering process. The arrangement includes apparatuses and methods that parallelize computations of two FI functions in KASUMI rounds within one clock cycle and computes two consecutive FL functions in the KASUMI rounds within one clock cycle.

Abstract: A method and system is provided for enhancing an audio signal based on spectral subtraction. The noise power spectrum for each frame of an audio signal is dynamically estimated based on a plurality of signal power spectrum values computed from a corresponding plurality of adjacent frames. An over-subtraction factor is then dynamically computed for each frame based on the noise power spectrum estimated for the frame. The signal power spectrum of the audio signal at each frame is then reduced in accordance with the over-subtraction factor computed for the corresponding frame.

Abstract: According to embodiments of the disclosed subject matter, cores in a many-core processor may be periodically tested to obtain and/or refresh their dynamic profiles. The dynamic profile of a core may include information on its maximum operating frequency, power consumption, power leakage, functional correctness, and other parameters, as well as the trending information of these parameters. Once a dynamic profile has been created for each core, cores in a many-core processor may be grouped into different bins according to their characteristics. Based on dynamic profiles and the grouping information, the operating system (“OS”) or other software may allocate a task to those cores that are most suitable for the task. The interconnect fabric in the many-core processor may be reconfigured to ensure a high level of connectivity among the selected cores. Additionally, cores may be re-allocated and/or re-balanced to a task in response to changes in the environment.

Abstract: According to some embodiments, an arrangement is provided for cooling a heat-generating device, including a memory module (e.g., a small outline dual inline memory module), in a system such as a laptop computer. The arrangement includes a heat spreader having a first section including at least one thermally conductive coupling member to thermally engage surfaces of electronic components on the heat-generating device and a second section including at least one spring member to cause pressurized engagement between the first section and the surfaces of the electronic components. The heat spreader may further be thermally coupled to a heat exchanger or a keyboard from which the heat is dissipated. Other embodiments are also described and claimed.

Abstract: Machine-readable media, methods, and apparatus are described to recover from stream under-run and/or over-run conditions. In some embodiments, an audio controller may discard any partial sample block of the stream.

Abstract: An arrangement is provided for an external agent to initiate data prefetches from a system memory to a cache associated with a target processor, which needs the data to execute a program, in a computing system. When the external agent has data, it may create and issue a prefetch directive. The prefetch directive may be sent along with system interconnection transactions or sent as a separate transaction to devices including the target processor in the system. When receiving and recognizing the prefetch directive, a hardware prefetcher associated with the target processor may issue a request to the system memory to prefetch data to the cache. The target processor can access data in the cache more efficiently than it accesses data in the system memory. Some pre-processing may also be associated with the data prefetch.

Abstract: An arrangement is provided for a black box recorder using machine check architecture in system management mode. A machine check architecture collects and registers the collected status and error information. After receiving an interrupt, a black box recording mechanism records the registered error information.

Abstract: An arrangement is provided for data value recovery in an optimized program by precisely allocating predicate registers to guard branching instructions in the optimized program at compilation time. At execution time, an execution path leading to a recovery point is determined based on values of predicate registers guarding branching blocks. The values of non-current and non-resident data may be recovered at the recovery point according to the determined execution path. Optimization annotations may also be utilized for data value recovery.

Abstract: Systems and methods of managing memory devices provide for reduced power consumption and better thermal management through enhanced memory throttling. In one embodiment a memory unit includes a memory device and a temperature measurement module coupled to the memory device. The temperature measurement device measures the internal temperature of the memory device. Memory throttling can therefore be implemented based on more accurate measurements and with a much shorter response time.