Patents Represented by Attorney Guojun Zhou
  • Patent number: 7275033
    Abstract: A method and system for providing a class-based statistical language model representation from rule-based knowledge is disclosed. The class-based language model is generated from a statistical representation of a class-based rule net. A class-based rule net is generated using the domain-related rules with words replaced with their corresponding class-tags that are manually defined. The class-based statistical representation from the class-based rule net is combined with a class-based statistical representation from a statistical language model to generate a language model. The language model is enhanced by smoothing/adapting with general-purpose and/or domain-related corpus for use as the final language model. A two-pass search algorithm is applied for speech decoding.
    Type: Grant
    Filed: September 30, 2000
    Date of Patent: September 25, 2007
    Assignee: Intel Corporation
    Inventors: Yibao Zhao, Yonghong Yan, Zhiwei Lin
  • Patent number: 7274372
    Abstract: A real-time digital engraving technique gives the appearance of traditional copperplate engraving. The present system accepts a 3D mesh comprising vertex data and applies a novel algorithm to generate a digital engraving image based on the mesh. The present method works on any 3D model, generates the resulting image in real-time, allows the user to dynamically change views, and does not require user intervention.
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: September 25, 2007
    Assignee: Intel Corporation
    Inventors: Adam T. Lake, Carl S. Marshall, Marc S. Blackstein, Daniel Johnston
  • Patent number: 7272274
    Abstract: A chassis includes a plurality of slots to receive modules. The chassis includes an electrical backplane to couple to a module received in a first slot of the plurality of slots. The module to couple via a first communication interface on the module. An optical backplane is also included in the chassis. The optical backplane is to couple to the modules via a second communication interface on the module. The optical backplane is to couple to the second interface on the module via at least one interconnect through an opening in the electrical backplane. The interconnect configured to couple a fabric interface associated with the second communication interface to a communication channel routed over the optical backplane.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: September 18, 2007
    Assignee: Intel Corporation
    Inventors: Robert J. Albers, Edoardo Campini, Hassan Fallah-Adl
  • Patent number: 7243249
    Abstract: A method and apparatus for facilitating power state control and awareness of an autonomous subsystem in a computer based system without involvement of the main operating system.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: July 10, 2007
    Assignee: Intel Corporation
    Inventors: Robert Dunstan, Frank P. Hart, Paul Zurcher
  • Patent number: 7243176
    Abstract: Transmission of digital signals across a bus between an electronic device having a transmitter and another electronic device having a receiver with termination for both the transmitter and receiver being referenced to ground, such that the electronic device having the transmitter and the other electronic device having the receiver are able to be powered with differing decoupled voltages, such that the voltage employed by the electronic device having the transmitter is able to be lower than the voltage employed by the other electronic device having the receiver, and wherein the electronic device having the transmitter may transmit addresses and/or commands to the other device having the receiver using single-ended signaling, while both electronic devices may exchange data using differential signaling.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: July 10, 2007
    Assignee: Intel Corporation
    Inventors: Hing Yan To, Joe Salmon
  • Patent number: 7230190
    Abstract: Some embodiments of the invention include an apparatus and system for keyboard arrangements where one or more of the keys are adjustable. In some embodiments, the arrangement includes one or more keys and a moving mechanism for controlling the position of the keys. The keys may be adjusted in terms of height. The adjustment in height may result from the operation of a lever or switch, or as a result of opening the case or shell of the system. Other embodiments are described.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: June 12, 2007
    Assignee: Intel Corporation
    Inventors: Wah Yiu Kwong, Hong W. Wong
  • Patent number: 7203368
    Abstract: A pattern recognition procedure forms a hierarchical statistical model using a hidden Markov model and a coupled hidden Markov model. The hierarchical statistical model supports a pa 20 layer having multiple supernodes and a child layer having multiple nodes associated with each supernode of the parent layer. After training, the hierarchical statistical model uses observation vectors extracted from a data set to find a substantially optimal state sequence segmentation.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: April 10, 2007
    Assignee: Intel Corporation
    Inventor: Ara V. Nefian
  • Patent number: 7197521
    Abstract: An arrangement is provided for using bit vector toggling to achieve concurrent mark-sweep garbage collection in a managed runtime system. A heap may be divided into a number of heap blocks. Each heap block may contain a mark bit vector pointer, a sweep bit vector pointer, and two bit vectors of which one may be initially pointed to by the mark bit vector pointer and used for marking and the other may be initially pointed to by the sweep bit vector pointer and used for sweeping. At the end of the marking phase for a heap block, the bit vector used for marking and the bit vector used for sweeping may be toggled so that marking phase and sweeping phase may proceed concurrently and both phases may proceed concurrently with mutators.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: March 27, 2007
    Assignee: Intel Corporation
    Inventors: Sreenivas Subramoney, Richard Hudson
  • Patent number: 7197628
    Abstract: A method and apparatus for utilizing multiple microcode flow synonyms or hardware flow synonyms for an instruction is disclosed. In one embodiment, a microcode synonym is created for execution on two or more execution units of differing types. One microcode synonym may be chosen for execution depending upon the availability status of the execution units. In another embodiment, several microcode synonyms may be chosen for execution. The results of the first microcode synonym to complete execution may be retired. If the results of execution of two microcode synonyms do not match, a fault exception may be raised.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: March 27, 2007
    Assignee: Intel Corporation
    Inventor: John W. Mates
  • Patent number: 7194736
    Abstract: An arrangement is provided for improving the performance of a dynamic compiler, specifically for dynamically optimizing integer division operations. When a compiler receives an integer division code at runtime, the compiler dynamically profiles a divisor of the division code. The integer division code is then optimized based on the characteristics of the divisor, which are determined at runtime.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: March 20, 2007
    Assignee: Intel Corporation
    Inventors: Xiaohua Shi, Guei-Yuan Lueh, Zhiwei Ying
  • Patent number: 7165029
    Abstract: A speech recognition method includes use of synchronous or asynchronous audio and a video data to enhance speech recognition probabilities. A two stream coupled hidden Markov model is trained and used to identify speech. At least one stream is derived from audio data and a second stream is derived from mouth pattern data. Gestural or other suitable data streams can optionally be combined to reduce speech recognition error rates in noisy environments.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: January 16, 2007
    Assignee: Intel Corporation
    Inventor: Ara V. Nefian
  • Patent number: 7124229
    Abstract: A method and apparatus for improved performance for handling priority agent bus requests when symmetric agent bus parking is enabled is disclosed. In one embodiment, a modified priority agent may be used. The modified priority agent may assert an unused symmetric agent bus request when it asserts its priority agent bus request. When a symmetric agent parks on the bus, continually asserting its symmetric agent bus request, the assertion of the otherwise unused symmetric agent bus request may cause the symmetric agent to withdraw its symmetric agent bus request. This may reduce bus response time for subsequent modified priority agent bus requests.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: October 17, 2006
    Assignee: Intel Corporation
    Inventors: Jeffrey D. Gilbert, Harris D. Joyce
  • Patent number: 7103723
    Abstract: An arrangement is provided for improving the performance of a computing system, specifically for improving the efficiency of code cache management for a system running platform-independent programs with a small memory footprint. The code cache of such a system is continuously monitored during runtime. When a condition warrants performing code cache management, the priority-based code cache management is performed based on selective code garbage collection. The code garbage collection is conducted selectively for dead methods in the code cache based on probabilities of the dead methods being reused.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventor: Michal Cierniak
  • Patent number: 7089273
    Abstract: An arrangement is provided for using a stack trace cache when performing root set enumeration in a stack of a thread during garbage collection. During the first root set enumeration in the stack, full stack unwinding may be performed and a stack trace cache may be created to cache stack trace information relating to stack frames. Subsequent sessions of root set enumeration in the stack may access and copy parts or the entire cached stack trace information instead of performing full stack unwinding.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: August 8, 2006
    Assignee: Intel Corporation
    Inventors: Gansha Wu, Guei-Yuan Lueh
  • Patent number: 7072834
    Abstract: An arrangement is provided for an automatic speech recognition mechanism to adapt to an adverse acoustic environment. Some of the original training data, collected from an original acoustic environment, is played back in an adverse acoustic environment. The playback data is recorded in the adverse acoustic environment to generate recorded playback data. An existing speech model is then adapted with respect to the adverse acoustic environment based on the recorded playback data and/or the original training data.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: July 4, 2006
    Assignee: Intel Corporation
    Inventor: Guojun Zhou
  • Patent number: 7058575
    Abstract: An arrangement is provided for integrating graph decoder with keyword spotting to improve the robustness of speech recognition. When a graph decoder based speech recognition mechanism fails to recognize a word sequence from input speech data, a keyword based speech recognition mechanism is activated to recognize the word sequence based on a set of keywords that are detected from the input data.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: June 6, 2006
    Assignee: Intel Corporation
    Inventor: Guojun Zhou