Abstract: Method for efficiently and flexibly comparing a group of multi-bit binary fields with a multi-bit expected pattern to generate a set of final match results, one final match result for each binary field in the group. Sets of of bit-wise comparator results are generated, one set for each binary field, by comparing each binary field with the expected pattern. Then, sets of bit-wise mask results are generated for each binary field by bit-wise masking each set of bit-wise comparator results with a mask pattern. Then, a set of preliminary match results is generated. Each preliminary match result is equal to the logical AND of all bits making up the bit-wise mask result set for the corresponding binary field. Then, a set of secondary match results is generated by negating all of the preliminary match results if a negate indicator is asserted.

Abstract: Circuitry for detecting signal patterns on a multi-bit bus. First comparison circuitry monitors a first portion of the bus comparing it with a first expected signal pattern, generating a first comparison output. Second comparison circuitry monitors a second portion of the bus comparing it with a second expected signal pattern, generating a second comparison output. Both comparison outputs are applied to an AND gate and a first OR gate. One data input of a multiplexer is coupled to the output of the first OR gate. Another data input is coupled to the output of the AND gate. Another data input is coupled to the first comparison output, and another data input is coupled to the second comparison output.One input of a second OR gate may be coupled to the multiplexer output, and another input coupled to a disable indicator, allowing the multiplexer output to be overridden.

Abstract: User-configurable diagnostic hardware contained on-chip with a microprocessor for the purpose of debugging and monitoring the performance of the microprocessor. Method for using the same. A programmable state machine is coupled to on-chip and off-chip input sources. The state machine may be programmed to look for signal patterns presented by the input sources, and to respond to the occurrence of a defined pattern (or sequence of defined patterns) by driving certain control information onto a state machine output bus. On-chip devices coupled to the output bus take user-definable actions as dictated by the bus. The input sources include user-configurable comparators located within the functional blocks of the microprocessor. The comparators are coupled to storage elements within the microprocessor, and are configured to monitor nodes to determine whether the state of the nodes matches the data contained in the storage elements.

Abstract: An expert system for diagnosing data communication networks. The expert system operates according to a landmark data abstraction paradigm, wherein landmarks are interpretations of network data. The landmarks are indicators of network problems. The expert system diagnoses the data communication networks by detecting landmarks and then interpreting the detected landmarks to determine whether network problems exist.

Abstract: A method for rendering a three-dimensional image on a computer graphics display device involving the steps of providing a data base defining at least the geometry and reflectivity of light emitters and object in the scene and approximating surfaces of each object in the scene as patches in three dimensional space. Each patch is approximated as one or more elements defined by vertices. A source of irradiated light in the scene is selected and defined as a light source. Then, for each vertex, a form factor representing the fraction of light energy that arrives at the vertex from the source is determined by ray tracing from the vertex to the source. Radiosity is then determined at each vertex based on the form factors determined for each vertex. This process is repeated a selected number of times using a different light source each time. In this manner a plurality of radiosities are determined that collectively indicate the global illumination of the scene.

Abstract: A clocking methodology for VLSI chips which uses global overlapping clocks, locally or remotely generated non-overlapping clocks, combined with pipeline control signals to generate signals which control the transfer gates of registers in a pipeline. The signals which control the transfer gates of the registers in a pipeline maintain the important timing relationships of the non-overlapping clock signals combined with the control signals. The global overlapping clocks are used where possible to provide timing advantages, while the non-overlapping clocks are used to eliminate race conditions as data propagates down a pipeline of transparent registers. Overlapping clock signals are used whenever such race conditions can be avoided, as at the ends of the registered pipeline, with the resultant performance improvement.

Abstract: A circuit for performing window-relative dithering of intensity data comprises a programmable dither cell; circuitry for comparing dither values stored in the dither cell with selected parts of the intensity values and outputting an increment signal in accordance with the results of the comparison; a wrap prevention circuit for preventing the intensity from being incremented if incrementing would cause the intensity to wrap to a low value; and an adder for incrementing the intensity in response to the increment signal, provided it is not inhibited by the wrap prevention circuit. The dither circuit may be advantageously employed in a computer graphics system to dither pixel intensity values.

Abstract: A configurable self-test circuit for a RAM embedded in an integrated circuit chip comprises an incrementable address register, a configurable control circuit, a write register, a signature generator, and a scanpath. The address register stores the current RAM address to be accessed and is adapted to automatically increment the RAM address by an address increment upon receiving an increment signal. The configurable control circuit has a normal operation mode and three test modes wherein all writes, all reads or alternating writes and reads are performed. The write register stores data patterns which are to be written to the RAM under test. The signature generator receives data read from the RAM and produces a unique signature in response thereto. A scanpath through the address register, control circuit, write register, and signature generator allows test vectors to be serially shifted in and test data to be shifted out of these devices. A full functional test is performed of the RAM.

Abstract: Shadow testing of a two dimensional projection of a three dimensional scene is accelerated by superimposing the projection with a plurality of scan areas, then examining points, and edges of objects, falling within each scan area. Points are identified as potentially shadowed points if bracketed by edges of any object, and the bracketing object is identified as a potential shadower of the potentially shadowed points. Potential shadowers and potentially shadowed points undergo a series of tests to rapidly determine which, if any, of the potential shadowers are actual shadowers of each potentially shadowed point.

Abstract: A memory device having a plurality of read ports which can be dumped simultaneously without affecting the data stored in the memory cells of the memory device. The read ports of the memory device of the invention include dump circuits comprising a pair of small NFETs which logically AND the values stored in the memory cell with a READ input signal and then pull low a precharged output line only when both of these signals are true. Each such read port dump circuit is electrically isolated from the others so that multiple read ports can be dumped simultaneously with affecting the data stored in the memory device. Also, by placing only a single transistor in the read port discharge path, the dump circuit may be small and have a minimal impact on write setup time in accordance with the invention.

Abstract: A method of moving blocks of pixel data, including window-identifying data, from a source area to a destination area within a frame buffer in a computer graphics system comprises the steps of: reading a block of pixel data from the source area into a pixel cache memory; combining source tiles with destination tiles in the cache; comparing pixel window identifiers read from the frame buffer with a pixel window identifier previously stored in the memory to determine whether the pixel window identifiers read from the frame buffer match the previously stored pixel window identifier; discarding each pixel whose corresponding window identifier does not match the previously stored window identifier; and updating the frame buffer with the pixel data not discarded.

Abstract: A silicon starting material for fabricating integrated circuits is desrcibed that comprises a silicon wafer substrate material and a first epitaxial layer grown on the wafer substrate which eliminates stacking faults in the subsequent fabrication of a semiconductor device.

Abstract: A three-dimensional pixel cache for use in a computer graphics system comprises source, pattern, and destination tile caches and a barrel shift register, or rotator, that serves as an interface between the tile caches and a frame buffer. The rotator has the capability of performing three types of rotation of data read/written from/to the tile caches horizontal rotation, vertical rotation, and rotation of nibbles within each pixel.

Abstract: Antialiased vectors, composed of a plurality of pixels along the vector minor axis for each major axis step, are rendered such that consecutively rendered pixels are always adjacent. For each major axis step, pixels are rendered along the minor axis in an order that reverses with each major axis step.

Abstract: A polygon rendering circuit for a computer color graphics system comprising an edge stepper which steps along edges of an input polygon to determine the span of the polygon along each scan line intersected by the polygon. The coordinate values of the edges on each scan line are determined to sub-pixel resolution such that only those pixels whose centers lie within the true polygon edges (within the span width) must be drawn. Processing efficiency is improved and bandwidth is minimized by passing only those edges of the polygon which are new to that polygon and by computing the Z values in the same manner as, and in parallel with, the X values. Improved results are also possible in accordance with the technique of the invention, for since adjacent polygons compute the same edge by stepping, there can be no gaps between polygons due to round-off errors.

Abstract: A system and method are disclosed for automatically configuring the interconnection of circuit boards in slots on the backplane of a computer. Some signal lines, such as bus grant and interrupt acknowledge signals, must be daisy-chained, or connected in series through the circuit boards collectively. However, if a circuit board is not present, then the daisy-chain is broken. For each slot to be monitored in the backplane, the present invention envisions implementing a generator, a valid logic level detector and a signal selector. The generator imposes an invalid logic signal onto an output connector of a slot to derive an input for the valid logic level detector. Based upon the input, the detector determines whether a circuit board resides in the slot. Accordingly, the detector adjusts the signal selector to either bypass the slot or connect the slot, as well as the present circuit board, to the daisy-chain.

Abstract: A floating point processor in which floating point register file write enables are self-timed from the exception flags from the respective floating point processing units. This self-timing is achieved by forming the floating point processing units from self-timed logic gates which gate data in accordance with the values of the data itself. In other words, the output of a logic gate is made valid only when all inputs to the logic gate have been evaluated as being valid. Since the floating point exception signals from the floating point processing units are also self-timed and no longer edge triggered, the results of the floating point operation may be written to the register file on the same phase in which the result and the exception flags become valid, thereby allowing processing latency to be reduced by a state. Hence, if there is a floating point exception during a floating point operation, the register cell is not written.

Abstract: Methods and apparatus for rendering graphics primitives to display devices in a computer graphics frame buffer system are disclosed. The methods provide an array of addressable video random access memory (VRAM) chips associated to form the graphics frame buffer. The VRAMs in the frame buffer are addressed with coordinate pixel locations on the display device corresponding to locations of the graphics primitives on the display device. The frame buffer is accessed with a graphics rendered according to arbitrarily shaped tiles containing pixels such that the pixels within the tiles have potentially different VRAM addresses.

Abstract: A system for generating an analog regulating voltage to be supplied to one or more circuit elements on an integrated circuit. The circuit elements have operational characteristics that are voltage dependent and the analog regulating voltage having the a property of changing with temperature, power supply voltage, and manufacturing process variations so as to substantially eliminate the effects of such variations on the operational characteristics of the circuit elements.

Abstract: Methods and apparatus for maximizing column address coherency for serial and parallel port accesses to a dual port frame buffer. Performance of the serial port of the frame buffer is greatly improved by separating the page boundaries in the horizontal direction (i.e., scan line organized), while performance of the parallel port of the frame buffer is enhanced by organizing the page boundaries for rectangular areas of the display. Performance at both ports may be maximized at the same time by organizing the video random access memory (VRAM) into tiles and vertically barrel shifting the scan line data at a fixed interval across the video display. During operation, the serial port output looks like an entire row of data while it has actually output parts of N rows of data from two separate rows of memory chips which are changed at the fixed interval. This approach allows the parallel port to organize columns N times higher in the vertical direction.