Abstract: An apparatus for converting a video input signal representing an image from a first format to a prescribed second format. The apparatus comprises the following elements: a sync separator (30) for extracting a synchronization (sync) signal from the video input signal; a section (32, 34, 36, 40) for generating a sample clock signal on the basis of the sync signal and the said prescribed format; a sampling section including A/D convertors (18a, 18b, 18c) for sampling the video input signal in accordance with the sample clock signal to obtain a prescribed number of samples per line of the image; a section (20a, 20b, 20c, 22) for combining the samples of at least two different lines to obtain a prescribed number of new lines each of which comprises the said prescribed number of samples per line; and a filtering section (17a, 17b, 17c) for filtering the video input signal so as to effectively horizontally average each line of the image.

Abstract: System and method for distinguishing duplicate source address replies caused by interconnecting devices connected to a local area network and duplicate source address replies caused by non-interconnecting devices connected to the local area network.The present invention may be implemented through an analyzer. The method includes the following steps: In step 1, the present invention sends a first Address Resolution Request packet for a first Internet Protocol target address. In step 2, all Internet Protocol source address responses replying to the first Address Resolution Request packet are catalogued in a first reply set. In step 3, a second Address Resolution Request packet for a second Internet protocol target address is sent on to the network. In step 4, all Internet Protocol source address responses replying to said second Address Resolution Request packet are catalogued in a second reply set. In step 5, the first reply set is intersected with the second reply set resulting in an intersection set.

Abstract: Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

Abstract: A method and apparatus for interpolating pixels to be displayed on a display screen so as to account for the nonlinearity of distance changes in the perspective projection of a 3-D object onto the display for corresponding linear distance changes in 3-D world space. Each pixel of an input polygon to be displayed on the display screen is given a perspective value in world coordinates for each display point, and this value is passed through the graphics processor along with the shading parameters associated with the each display point. The respective shading parameters for each display point are then scaled by the perspective value for each display point to account for the effects of perspective foreshortening of the displayed object on the display screen. Since no translation to world coordinates is required for the perspective scaling, fast hardware circuitry may be used.

Abstract: Methods for texture mapping graphics primitives in a graphics pipeline architecture system. The methods utilize rectangular box filters to down-sample original texture maps thereby optimizing aliasing and blurring when graphics primitives have a two-dimensional texture mapped to a three-dimensional object. The methods of texture mapping graphics primitives in a frame buffer graphics system comprise the steps of determining an original texture map of two dimensions for a surface, storing the original texture map in the frame buffer, sampling the original texture map independently using an asymmetrical filter to construct multiple versions of a texture and to address textured pixels on a display in the frame buffer graphics systems, mapping the textured pixels to areas on the frame buffer, and displaying the textured graphics primitives on the display. A technique for addressing textured pixels stored in a rectangular texture (RIP) map is also described.

Abstract: Apparatus for receiving and automatically storing data words according to magnitude is provided. A self-sorting stack embodying the invention comprises a sorting device comprising means for simultaneously comparing the incoming data with the contents of each stack register, and logic and switching means for automatically inserting the new data into the correct register on the stack while at the same time pushing the contents of that and subsequent registers down one location. The entire operation is performed in one clock cycle, the same as for a conventional nonsorting stack.

Abstract: A scan conversion algorithm for rendering antialiased vectors in a multi-processor graphics system comprises the following steps: providing signals to the processors indicative of scan lines the respective processors are responsible for, determining a first set of storage pixels to be rendered by the processors, rendering such storage pixel of the first set simultaneously, each by a different processor, determining a second set of storage pixels to be rendered, and rendering each of the second set of storage pixels substantially simultaneously by a different one of the processors. The determinations of the first and second sets of storage pixels are made in accordance with the signals indicative of scan lines for which the respective processors are responsible.

Abstract: The present invention is a time vernier providing fine timing control of an input signal having coarse timing edges. The time vernier comprises a receiving means for receiving a value representing a desired time delay to be added to the coarse timing edge input. The desired time delay may have both fine and coarse delay aspects. The time vernier also comprises a first decoding means for decoding the fine delay aspect and generating fine delay control signals, as well as a second decoding means for decoding a coarse delay aspect and generating coarse delay control signals. A delay line is also included in the time vernier which has inputs to receive the input signal having coarse timing edges, the fine and coarse delay control signals, and a control voltage which automatically adjusts with temperature and power supply variations, so as to provide for temperature and power supply compensation. The delay line combines the fine and coarse delay signals to provide an output signal with fine timing edges.

Abstract: A logic system uses novel mousetrap logic gates which implement novel vector logic. In a vector logic system, any number of valid vector logic states and one invalid vector logic state is defined by the logic signals on a set of logic paths. An invalid vector logic state is defined as the case when all logic paths exhibit a low logic signal. A valid vector logic state can be defined in a variety of ways. In the preferred embodiment, a valid vector logic state is defined as the case when one and only one of said logic paths exhibits a high logic signal. Furthermore, mousetrap logic gates, which can be connected directly in series and/or parallel to collectively perform logic functions, implement the foregoing logic scheme. Each mousetrap logic gate has an arming mechanism, ladder logic, and a buffer. A precharge is supplied by the arming mechanism to the buffer. Incoming logic is operated upon by the ladder logic and used to trigger the precharged buffer.

Abstract: Disclosed is a system that monitors the signal strength of each transmission by a node on a LAN cable of a local area network and determines the location of the node sending the signal. This system has a monitor at each end of the LAN cable, with one of the monitors typically being located in a computer node attached to the cable. When an information frame is sent on the cable, each of the monitors records the signal strength of the frame preamble and the source address contained within the frame. The distance to the node from a first end of the cable, expressed as a percentage of the length of the cable, is the ratio of the signal strength at the second end of the cable to the sum of the signal strengths.

Abstract: A recycling ramp interpolator is described which can provide multiple measurements for a single input trigger signal by maintaining initial input waveform reference and interpolating multiple times before completely discharging. The interpolator reference voltage can be changed to provide effective sampling intervals of fractions less than one of the clock period.

Abstract: A method of moving blocks of pixel data, including window-identifying data, from a source area to a destination area within a frame buffer in a computer graphics system comprises the steps of: reading a block of pixel data from the source area into a pixel cache memory; combining source tiles with destination tiles in the cache; comparing pixel window identifiers read from the frame buffer with a pixel window identifier previously stored in the memory to determine whether the pixel window identifiers read from the frame buffer match the previously stored pixel window identifier; discarding each pixel whose corresponding window identifier does not match the previously stored window identifier; and updating the frame buffer with the pixel data not discarded.

Abstract: An apparatus and method for monitoring voltage on a LAN cable on which data is conveyed by negative-going pulses. Positive voltage on the LAN cable is interpreted as noise. Positive voltage is detected by, for example, comparing the voltage on the LAN cable to a positive reference voltage, determining the peak positive voltage on the LAN cable, or determining the average positive voltage on the LAN cable. Upon the detection of positive voltage on the LAN cable, the presence (and possibly the amount) of noise is indicated to a person or data processing system which supervises the LAN called a LAN sentinel. The apparatus or method could be implemented in a Media Attachment Unit (MAU) with audio, visual or electronic noise indication means. Alternatively, it could be implemented as a hand-held diagnostic tool.

Abstract: Pixel arithmetic and logical units for rendering pixels in graphics systems. Circuits for performing arithmetic operations on raster scan data are provided. The circuits comprise opcode registers for selecting an arithmetic function which transforms pixel value data corresponding to graphics primitives, multiplication circuits interfaced with the opcode registers for multiplying graphics operators with graphics data to obtain transform pixel value data, combining circuits interfaced with the multiplication circuits for adding transform pixel value data to existing pixel value data and processing circuitry interfaced with the combining circuitry for storing overflow data from the combining circuitry when adding transform pixel data overflows the combining circuitry.

Abstract: A method of producing a microchip having at least a portion of an electrical circuit element contained within a hermetically sealed enclosure comprising the steps of: forming a cavity in a first substrate assembly which has a cavity opening at a first surface portion of the first substrate assembly; forming an electrical circuit element and sealing ring from a film applied to a first surface portion of a second substrate assembly with the sealing ring arranged in circumscribing relationship with at least a portion of the circuit element; positioning the first surface portion of the first substrate assembly opposite the first surface portion of the second substrate assembly with the sealing ring located in circumscribing relationship with the cavity opening; sealingly bonding the sealing ring to the first surface portion of the first substrate assembly.

Abstract: A color encoder for reducing visible artifacts even when the values of the respective color signals are truncated during encoding. Since the human eye is most sensitive to luminance variations in the displayed image, luminance errors (and hence visible artifacts) are minimized by adding red and green color error signals to the blue color intensity signal prior to encoding so that luminance detail may be maintained. The blue channel is chosen for this purpose since the human eye is least sensitive to changes in blue and yellow. The color maps for the resulting encoded signals may be scaled such that the red and green values are raised and/or the blue values lowered so as to maintain the same relative intensity of luminance in the displayed image. Errors in the displayed luminance signal may thus be made up to four times smaller without increasing the amount of memory required and without adding expensive processing circuitry.

Abstract: The present invention is directed to a buffer/inverter which generates symmetric and complementary output signals from a single input signal. The device employs four inverters having similar switching speeds. The true output signal is generated by passing the input signal through two inverters. The complement output signal is generated by passing the true output signal through a third inverter, passing the input signal through a fourth inverter and coupling the outputs of the third and fourth inverters.

Abstract: The disclosed photoresist process employs an i-line peak containing light source, such as that of the mercury spectrum, in conjunction with a dye capable of both absorbing i-line light and withstanding subsequent those baking procedures employed in producing portable-conforming-mask (PCM) photoetchings. Applicant has found that a series of butadiene or bromine substituted butadiene dyes in general, and N,N'-Dibutyl-N,N'-Di (1-(4,4-dicyano-1,3-butadiene))-1,6-hexanediamine, in particular, are particularly well suited to these purposes. Such dyes are most preferably used in conjunction with a second dye capable of absorbing of a non-i-line light source used to expose a bottom photoresist layer of a PCM system.

Abstract: A method and device for improving the processing performance of a transform engine by off-loading the processing of those input polygons which have no more than a predetermined number of edges and decomposing such polygons into trapezoids which can be rendered by a scan conversion system. This is accomplished in accordance with the invention by reading edge data of each input polygon into a RAM and determining the relative positions of the Y coordinates of end points of each edge so that the beginning and end of each respective edge of the polygon in the Y direction may be determined. The polygon is then broken into trapezoids by reading in the respective beginning points of respective edges of the polygon and proceeding until the end point of one of the edges is reached. At the end of one edge, another edge of the polygon is read in, and the process continues until all trapezoids in the polygon have been drawn.

Abstract: A recycling ramp interpolator is described which can provide multiple measurements for a single input trigger signal by maintaining initial input waveform reference and interpolating multiple times before completely discharging. The interpolator reference voltage can be changed to provide effective sampling intervals of fractions less than one of the clock period.