Abstract: All the address lines in a data processing system can be tested by using one or more small memory device that do not occupy the full addressing capability of the address lines. In one embodiment, some of the address inputs of the memory device is connected to different address lines at different times. Instructions are pre-loaded into some locations of the memory device such that the address lines has to be asserted to fetch the instructions for execution. By executing the instructions and appropriately connecting the address lines to the address input, all the address lines can be tested. In another embodiment, some of the locations are pre-loaded with a set of predetermined values. A program then writes another set of predetermined values to associated locations. By reading the values in the locations and compared with the sets of predetermined values, it is possible to determine if the address lines are functioning properly.

Abstract: A wireless programmable logic device contains a wireless component and a programmable logic component. A remote wireless host can be used to program the programmable logic device. Some product designs require multiple programmable logic devices. When wireless programmable logic devices are used in the design, all of them can receive data and commands from the host. As a result, the wireless host can control the order of configuration and the start time of these logic devices. There is no need to build glue logic for this purpose. Consequently, the efficiency in product design is improved. If there are problems in programming a programmable logic device, the host can log the failed operation in its memory. This information could be used to improve production flow.

Abstract: A thyristor-based semiconductor device includes a filled trench separating and electrically insulating adjacent thyristor control ports. According to an example embodiment of the present invention, the filled trench is formed in a substrate adjacent to at least one thyristor body region. The filled trench includes a conductive filler material, an insulative material formed on the conductive filler material and at least two laterally-adjacent thyristor control ports separated from one another by the conductive filler material and the insulative material. One of the control ports is adapted for capacitively coupling to the thyristor body region for controlling current in the thyristor. With this approach, two or more control ports can be formed in a single filled trench and electrically isolated by the conductive filler material/insulative material combination.

Abstract: The present invention allows a designer to easily re-target the design optimized for the device of one integrated circuit vendor to the device of another vendor. The designer can start with a set of post-routed boolean equations optimized for a certain target integrated circuit. The present invention allows the automatic generation of a synthesizable, editable, and simulatable HDL description. The designer may edit the HDL code. Another target may be selected. Design optimization and placement and routing can be performed for the new target.

Abstract: One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable fabric. Other components in the transceivers can have options that are controlled by the programmable fabric. The integrated circuit may also contain one or more processor cores. The processor core and the transceivers can be connected by a plurality of signal paths that pass through the programmable fabric.

Abstract: A data conveyance integrated system that can be utilized in a base station and/or end user devices in a wireless communication system. The integrated system includes first and second integrated circuits (ICs). The first IC includes a first serial-deserial (SERDES) module, a transmit radio frequency module, and a receive radio frequency module. The transmit and receive radio frequency modules provide the wireless communication between the base stations and end user devices. The second IC includes a second SERDES module and a programmable logic fabric programmed to implement one or more wireless communication functions. Accordingly, the programmable logic fabric generates outbound digital signals from data (e.g., video, audio, control, or text data) provided to the device, and/or processes inbound digital signals to recapture the originally transmitted data. Thus, base stations and/or end user devices within a wireless communication system can be readily reconfigured.

Abstract: Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an iterative process of changing the structure of the network and/or the associated parameters. Specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.

Abstract: A method for completing the routing of a partially routed design is provided. The unrouted pins are routed to generate a first plurality of nets that may contain shorts or overlaps between the nets. The nets are analyzed to obtain timing information, and then divided into a set of critical and a set of non-critical nets. The non-critical nets are hidden, and the critical nets are rerouted to remove overlaps. The non-critical nets are then unhidden. The non-critical nets and rerouted critical nets are then rerouted so as to remove overlaps.

Abstract: Method and apparatus are described for providing a rule file. More particularly, a design rule document is converted to a table file of design rules and associated design rule values, where design rules follow a naming convention to maintain uniqueness among them. A parameterized design rule check (PDRC) file is obtained. Such a PDRC file calls out design rule names instead of design rule values. A computer program is used to exchange design rule values associated with design rule names in the table file for the design rule names called out in the PDRC file to provide a design rule check (DRC) file. This method and apparatus also apply to any technology file containing parameterized rules.

Abstract: An on-chip error correction circuit can be used to correct errors in memory cells of a FPGA. In one embodiment of the invention, the circuit can compute, during configuration, a plurality of error correction bits. These error correction bits are stored in a designated location on the FPGA. After all the memory cells are configured, the error correction circuit continuously computes the error correction bits of the memory cells and compares the result to the corresponding values stored in the designated location. If there is discrepancy, the stored error correction bits are used to correct the errors. In another embodiment of the invention, a plurality of parity bits of the original configuration bits is calculated. These parity bits are stored in registers. The FPGA contains on-chip parity bit generators that generate the corresponding parity bits. A discrepancy between the generated and stored parity triggers error correction action.

Abstract: A transceiver can be used to send and receive data at a lower data rate than the data rate its SERDES is designed to operate. It contains a transmitter interface that receives a first set of data at a lower data rate and delivers a second set of data to the SERDES at a higher data rate. The transceiver also contains a receiver interface that receives a third set of data from the SERDES at the higher data rate and delivers a fourth set of data at the lower data rate. To reduce the minimum transmission serial data rate, one embodiment of the present invention derives a half-speed clock for the transmitter interface. Using the half-speed clock, the transmitter interface supplies data to be transmitted at half the normal rate with respect to a reference clock. As a result, the data rate is reduced. The opposite operation is used for the receiver interface.

Abstract: All the address lines in a data processing system can be tested by using one or more small memory device that do not occupy the full addressing capability of the address lines. In one embodiment, some of the address inputs of the memory device is connected to different address lines at different times. Instructions are pre-loaded into some locations of the memory device such that the address lines has to be asserted to fetch the instructions for execution. By executing the instructions and appropriately connecting the address lines to the address input, all the address lines can be tested. In another embodiment, some of the locations are pre-loaded with a set of predetermined values. A program then writes another set of predetermined values to associated locations. By reading the values in the locations and compared with the sets of predetermined values, it is possible to determine if the address lines are functioning properly.

Abstract: A single integrated circuit can be designed to include a processor core and one or more configurable peripheral devices selectable by a user. Because the peripheral device is configurable, the user can select only the features he/she needs in the integrated circuit. As a result, the peripheral devices included in the integrated circuit do not have to be flexibly designed in the same manner as commercially available peripheral devices. Consequently, they are easy to use.

Abstract: A method for customization of the software of an FPGA-based SoC includes the steps of selecting (380) a system component used for customizing the FPGA-based SoC, configuring (382) the selected system component with parameters for use with the FPGA-based SoC and propagating (384) the parameters used to configure the selected system component to peer system components. The method further includes the step of configuring (388) the peer system components using the propagated parameters during customization of the FPGA-based SoC and creating (401) a software interface to the selected system components and to the peer system components.

Abstract: A verification agent can be used to verify hard and/or soft modules under test in an integrated circuit. The integrated circuit contains a processor and memory for storing code executable by the processor. The module under test performs predetermined operations. The verification agent interacts with the module under test, including sending signals to the module under test and generating results based on the interaction. The code causes the processor to receive the results and compare the results with expected values. The module under test may be deemed to operate properly if the actual results match the expected values.

Abstract: An algorithm that includes delay elements is used for echo cancellation. The delays allow burst processing of consecutive samples of transmitting and receiving signals in a telephone communication system. As a result, there is tremendous reduction of memory bandwidth when compared to conventional sample-by-sample processing of signals. This algorithm can be advantageously implemented in FPGAs. Echo in over a thousand channels can be cancelled using a FPGA and an external memory device.

Abstract: The invention relates to a method for placing design components of an integrated circuit. A first site is selected. Other sites that are at maximum distances from already used sites may be selected. Components that have minimum connectivity to already placed components are selected. These components are used for preplacement. Preferably, the number of preplaced components is small. The rest of the design components are placed. An overlap ratio is computed. If the overlap ratio is above a predetermined value, the result is unplaced and additional components are preplaced. Another placement is performed. Overlap ratio is again computed. The steps of unplacing, adding preplaced components and computing overlap ratio are repeated until the overlap ratio falls below the predetermined value.

Abstract: The present invention is a programmable integrated circuit that can be used to handle different communication specifications. In one embodiment, the integrated circuit contains at least two physical layer modules, a media independent interface and a media access control module. The physical layer modules are preferably fixed logic components embedded in programmable logic fabric. In another embodiment, the integrated circuit contains a physical layer module and at least two media access control modules. The physical layer module is preferably a fixed logic component embedded in programmable logic fabric.

Abstract: A programmable integrated circuit can be designed to emulate, on demand, one of several commonly used microprocessors. It contains a configurable instruction processing unit and a superset datapath unit. The instruction processing unit further contains a configurable microcode unit and a non-configurable sequencing unit. The programmable integrated circuit can be programmed so that a microcode compatible with a target microprocessor is installed in the configurable microcode unit. The superset datapath unit is a superset of the datapath elements of all the target microprocessors.

Abstract: A wireless programmable logic device contains a wireless component and a programmable logic component. A remote wireless host can be used to program the programmable logic device. Some product designs require multiple programmable logic devices. When wireless programmable logic devices are used in the design, all of them can receive data and commands from the host. As a result, the wireless host can control the order of configuration and the start time of these logic devices. There is no need to build glue logic for this purpose. Consequently, the efficiency in product design is improved. If there are problems in programming a programmable logic device, the host can log the failed operation in its memory. This information could be used to improve production flow.