Abstract: A clamping circuit comprises a first transistor having a first and a second resistor shunting the base-collector and base-emitter junctions, respectively, and a second transistor opposite in polarity to the first transistor which has its emitter connected to the base of the first transistor. Externally, the clamping circuit has a connection from the collector of the first transistor to a first voltage level terminal, from the emitter of the first transistor to a voltage output terminal, and from the base of the second transistor to a reference voltage terminal. A second voltage level terminal is provided to which portions of the circuit, including the emitter of the first transistor and the collector of the second transistor, are connected.

Abstract: Polyoxide capacitors for semiconductor integrated circuits having oxide dielectric films of 500 Angstroms or less are fabricated using in-situ doped polysilicon layers to have electrical field breakdowns of from 6 to 9 MV/cm. The first polysilicon layer is formed by LPCVD using silane and phosphine at a temperature in the range from about 570 degrees C. to 595 degrees C.These capacitors are relatively precisely valued devices used particularly in applications such as filter/codecs. However, they are useful wherever integral capacitors are needed having high dielectric strength polyoxides, including such semiconductor integrated circuit devices as EPROMs and dynamic RAMs.

Abstract: In planar silicon semiconductor devices of the PN junction type, field plates overlie the silicon dioxide-silicon nitride film on the device surface to inhibit inversion formation of conductive channels on the device surface. The field plates are connected to a more heavily doped zone on one side of a PN junction and extend some distance over the lightly doped zone on the other side of the PN junction.At high reverse biases, the presence of trapping centers produces a charge level at the device surface, resulting in current channeling which produces excessive reverse leakage current. This effect is avoided or reduced by omitting the silicon nitride layer in a portion overlying the more lightly doped zone and spaced away from the PN junction boundary. This omission eliminates a portion of the oxide-nitride interface which appears to be the locus of such trapping centers.

Abstract: A method of liquid phase epitaxy is disclosed for growing a plurality of different layers on each of a plurality of semiconductor wafers during a single heating cycle. Each of a series of melts, each corresponding to a layer to be grown, is divided, in succession, into aliquant portions and a remainder portion. Each aliquant portion is contacted by one or more wafers, and epitaxial growth occurs as the temperature is lowered. Provision of a remainder portion enables a two-phase melt, and a wafer contacts only one distinct melt at a time.After a growth step, the next successive melt likewise is separated into aliquant portions and a remainder portion, the wafers are removed from the preceding melt chambers and placed in contact with the newly formed aliquant portions, and growth of another layer ensues from another drop in temperature. The process is repeated for each melt provided.Apparatus for carrying out the method also is described.

Abstract: A capacitor-resistor-capacitor (CRC) element for active filter realization, which is fully integrable and compatible with MOS technology, is described. The incorporation of the CRC element in a semiconductor integrated circuit active filter also is described. The structure of the CRC filter element is closely analogous to a depletion mode MOS field effect device, except that the channel zone 26 is doped to a level which substantially precludes conductivity modulation at the usual operating voltages. However, the doping level is such as to enable the use of the channel zone as a semiconductor resistance element. Thus, the N-channel CRC element realized in the NMOS technology comprises a first capacitance composed of the gate 27, gate dielectric 38, and resistive channel 26, paralleled by the resistive channel 26 itself constituting a resistor, and then the underlying PN junction capacitance between the N-type resistive channel 26 and the underlying P-type semiconductor body portion 21.

Abstract: The occurrence of pyramidal protrusions on the surface of GaAs and GaAlAs p-n junction wafers produced by a multislice liquid phase epitaxy process is avoided by slow cooling to a specified quenching temperature or below. The pyramidal protrusions are constituted of the silicon which is the amphoteric dopant used in these semiconductors. Pyramids are not formed if the epitaxial reactor is cooled at a rate of 1.degree. Celsius to 3.degree. Celsius per minute to a temperature less than about 140.degree. Celsius before the wafers are moved to the cool portion of the reactor and then further cooled to room temperature.

Abstract: A solar energy system for heating water is disclosed. The system comprises a closed piping circuit in which water is pumped through a heat exchanger and storage tank which are not exposed to freezing temperatures up through a solar collector which may be so exposed. Protection against damage from freezing is provided by enabling drain-back of the water from exposed portions of the system and replacement with air when there is no water circulation.When water is circulating, a surge pipe bypassing the storage tank provides unimpeded flow of the full volume of water while extracting entrained air which is conveyed to the storage tank. Thus, solar-heated water does not flow through and is not stored in the storage tank during operation of the system, and the cost and inconvenience of insulating the storage tank in order to inhibit large energy loss is avoided.

Abstract: A plastic encapsulation of the chip carrier type for a semiconductor integrated circuit is described. The package includes a lead frame member formed from a continuous metal tape which permits reel-to-reel automatic processing. The lead frame member provides the entire means for connecting from electrodes on the active or front surface of the semiconductor chip to contact members external to the encapsulation. The lead frame member also includes integral backside contact members providing electrical and thermal contact to the back surface of the semiconductor chip. The backside contact members similarly are integral with contact members external to the encapsulation. The interconnected structure including the lead frame member and semiconductor chip is housed in a molded plastic encapsulation. The package is capable of very small dimensions and is adapted for a high degree of automatic fabrication, including handling in stick-type magazines for subsequent operations such as testing, aging, and assembly.

Abstract: A semiconductor encapsulation of the chip carrier type has a collar-like protective housing member which encompasses the periphery of the chip carrier from which external lead members protrude. The protective housing member has a mating surface with a portion of the surface of the carrier. The interior of the protective housing member has recesses which accommodate the lead members singly, thus precluding their deformation.

Abstract: A circuit is provided in which the output current is the inverse, that is, the reciprocal, of the input current.The circuit comprises an input current branch and an output current branch, each branch including the emitter-collector electrodes of one of matching transistors, and a reference current branch containing a pair of serially connected, like poled, diode-connected transistors. The base electrode of the input branch transistor is connected to a node in the reference branch on one side of both diode-connected transistors, and the emitter of the output branch transistor is connected to a node in the reference branch on the other side of both diode-connected transistors. The base of the output branch transistor is connected to a node in the input branch on the emitter side of the input branch transistor.The circuit thus represents sums and differences of various voltages across the PN junctions in the several branches.

Abstract: A laser is coupled to an optical fiber in an hermetic encapsulation by locking a portion of the fiber near the laser in a body of solder. With the laser energized, the position of the optical fiber is adjusted within an aperture through the solder body to optimize the light output at the end of the fiber. The solder body then is heated to cause flow around the fiber and cooled to lock the fiber in position.

Abstract: A semiconductor device including a double cavity semiconductor chip carrier 100 which comprises a multilayer ceramic sandwich structure having a pair of semiconductor chip receiving cavities in the opposite faces thereof. The package enables mounting and electrical interconnection of a pair of semiconductor integrated circuit chips in a package of the same size as that for a single chip and having somewhat greater thickness.External terminals 93 on an outside face of the carrier are connected selectively by metallization paths 44, 53, 55, 83 integral with the carrier to chip mounting pads 41, 51 and to internal terminals 28 within the carrier. The internal terminals are disposed peripherally with respect to the chip cavities and adapted for interconnection with chip contact pads 26. Thus, a pair of unlike semiconductor integrated circuits can be interconnected in accordance with different patterns within a single package.

Abstract: Low resistance or ohmic contacts to p and n-type conductivity semiconductor material sometimes requires a different metal for each contact. Intermixing of these metals is undesirable so that special measures are necessary to form such contacts in close proximity on a common semiconductor surface.Using gold alloy contact materials, a first gold alloy is deposited on the common surface and defined by photolithography to make the contact to material of one conductivity type. The common surface and first contact then are covered by successive layers of titanium and gold. The titanium-gold layer is selectively etched by photolithographic means to expose the material of opposite conductivity type. A second gold alloy layer then is deposited on the exposed surface, and patterned photolithographically using an etchant which removes the gold and gold alloys but does not attack titanium. Finally, the titanium protective layer is removed using a selective etchant which does not attack gold or gold alloys.

Abstract: A contact structure to the light emitting surface 19 of a light emitting device 10 having an array of small distributed contacts 14 is made by selectively depositing a larger area bonding pad 15 over a portion of the distributed contacts. The small contacts not covered by the bonding pad then are removed by sputter etching and contact to the device is made by wire bonding a lead 17 to the bonding pad.

Abstract: Integrated circuit complementary transistors for high voltage switching applications are fabricated in separate dielectrically-isolated pockets (12), (14) of high resistivity silicon, supported in a conductive medium (11) such as polycrystalline silicon, using surface adjacent conductivity type zones constituting emitter (19), (23), base (16), (20) and collector zones (17), (21). In one embodiment using high resistivity (75-300 ohm cm) silicon, referred to as .pi. material, for the material of the pocket, one transistor is a PN.pi.P device, and the other is an NP.pi.N. In the PN.pi.P the reverse-biased base-collector pn junction is the interface between the N base zone (16) and the .pi. portion (12) of the collector zone. In the NP.pi.N transistor the base-collector junction is the interface between the lightly doped .pi. extension (14) of the base zone (20) and the N collector zone (21). A connection (32) is provided to the conductive substrate to enable application of a suitable potential thereto.

Abstract: A process is disclosed for gettering deleterious metal impurities, particularly the transition metals such as Cu, Fe, Co, Ni and Cr from silicon wafers by high temperature treatment for a comparatively short time in a hydrogen chloride vapor at low oxygen pressure. The low oxygen pressure inhibits the oxide growth on the silicon surfaces to thicknesses of not more than about 150 Angstroms, sufficient to protect the silicon surface but not so thick as to constitute a barrier to outdiffusion of the gettered impurities. This particular process may be preceded and followed by other previously known gettering techniques.

Abstract: A semiconductor varactor diode of the hyperabrupt junction type, typically having a PNN+ configuration, is disclosed. The impurity concentration in the intermediate N-type portion is grown in by the molecular beam epitaxy process to provide the hyperabrupt profile. Also, the N-type background doping in the P-type zone is minimized by the same epitaxial process to reduce the level of impurity compensation needed.

Abstract: A method of making MOS devices, primarily in integrated circuit form, is disclosed. Device areas first are defined on a silicon semiconductor chip, typically by means of a silicon nitride pattern 13A-13B. This pattern then is used to locate impurity introductions and to define areas of semiconductor surface portion removal. The latter operation produces mesas 16-17 coincident with the device areas. By this combination of steps and silicon oxide regrowth 27 where silicon has been removed, well-defined conductivity type zones are formed under the silicon oxide portions to function as buried terminal zones 28, 29, 30 of MOS devices. In the sole critical mask registration step, one edge 38 of the gate electrode 31 is located relative to the boundary 39 of a buried terminal zone 28. Finally, the channel zone 34 and the other terminal zone 33 of an MOS transistor are emplaced by a self-alignment process, followed by a heating step which adjusts final device dimensions.

Abstract: Semiconductor chips for certain types of devices must be extremely thin, typically less than two mils in thickness. They are therefore extremely fragile and difficult to handle. Such chips are provided with increased strength and rigidity by the addition of a deposited metal frame member on one surface of the chip encompassing the electrode pattern. The frame member has a thickness several times that of the electrode pattern.

Abstract: A heat conducting and radiating arrangement for an electronic assembly, which includes heat generating semiconductor devices, comprises a thermally conductive holder member 20 for the semiconductor device 13 which is conveniently clamped to a large area, heat radiating member 12. The holder member 20 is adapted to be mounted, secure from rotation, to a circuit board 11 to which the semiconductor device 13 is electrically connected.