Abstract: A silicon semiconductor integrated logic circuit of the injection or merged transistor logic type has output contacts in which ohmic and Schottky barrier portions are combined. A portion of the surface region of each output transistor collector is converted to more heavily doped N-type conductivity so that a metal contact applied thereto makes low resistance contact to the more heavily doped portions but forms a contact of the Schottky barrier type to the more lightly doped portion. The effect of the Schottky contact portion is to control minority carrier storage in the collector of the NPN output transistor by forcing the hole excess density at the Schottky portion surface to be zero thereby enabling short propagation delay time.

Abstract: A single-ended input full wave rectifier circuit is disclosed comprising a complementary common emitter amplifier configuration. An input signal comprising complementary pulses, such as a sine wave, causes conduction alternately in the collector circuits of the complementary transistors. One collector output voltage signal is inverted and applied across a load resistor across which the other alternately occurring collector output also is applied. The circuit output taken across the resistor is a series of same-going pulses constituting a full wave rectified version of the circuit input.

Abstract: A method is described for growing epitaxial layers of material on monocrystalline substrates, chiefly silicon, which are substantially free of slip dislocations. The method involves placing an encircling ring of inert, heat resistant material around the rim of the substrate and over the peripheral surface of the substrate to suppress radiation from the peripheral portion of the wafer. The generation of slip dislocations is inhibited because heat is more uniformly distributed throughout the wafer.

Abstract: A triode sputtering system comprises a plasma confining enclosure including a cathode at one end, an anode at the other, and a central plasma supporting portion. Contamination caused by unwanted sputtering of the surfaces of the confining apparatus is substantially eliminated by making the confining enclosure in several, typically four, electrically isolated portions, namely, the cathode support portion, the anode support portion and a pair of plasma support portions. In the structure described there is avoided the relatively large potential difference between the confinement enclosure and the plasma, which occurs predominantly at the anode support end of the confining enclosure of prior art one-piece apparatus. This portion of the apparatus has been found to be the major source of unwanted sputtering therein.

Abstract: A version of integrated injection logic is disclosed in which both the switching transistor and the current source transistor are of the vertical type and in which the logic gates are fabricated in the same semiconductor integrated chip with linear circuits which are based on the complementary bipolar integrated circuit technology.The injection logic gate is fabricated simultaneously with the linear integrated circuit using selected steps of the complementary bipolar technology. High voltage linear circuits and efficient logic circuits are achieved based on the use of a single moderate resistivity N-type epitaxial layer deposited on a high resistivity P-type substrate. In the logic circuit portion the epitaxial layer forms the collector zone of the current source transistor and the base zone of the switching transistor.

Abstract: A local battery feed circuit for telephone station sets comprises two half circuit portions substantially symmetric about an imaginary line midway between the TIP and RING telephone lines. Each half circuit includes a current drive amplifier including a pair of up-down emitter follower transistors and a driver transistor. A coupling capacitor and matched resistors provide common mode interference reduction without degrading differential mode signals. Power supply noise is substantially eliminated by transistors in each half circuit arranged to produce an a.c. current equal and opposite to that generated from the power source.

Abstract: A process for fabricating semiconductor devices is disclosed. In particular, a method for separating semiconductor wafers into device chips includes the step of forming a photoresist grid pattern underlying the metallization layer on the back face of the wafer. Mechanical means, such as scribing or sawing, are used to penetrate the metal layer, the underlying photoresist layer, and at least a portion of the semiconductor body. Separation then is completed either by breaking, further sawing or etching. The process enables a clean separation to be made through fairly heavy gold or gold alloy coatings which is particularly advantageous for devices which are to be eutectic-bonded to mounting platforms.

Abstract: A high speed bipolar noninverting current-mode logic AND gate is the basic building block for a current-mode logic family. The AND gate comprises a current steering differential pair of transistors, a pair of dual emitter input transistors, a dual emitter reference transistor, an output resistor and a fixed current source. The conducting state of the current steering transistor pair is so controlled that a logic "one" at the base electrodes of both input transistors produces a logic "one" at an output terminal taken from the collector electrode of the reference transistor. Further, a logic "zero" at both input transistors produces a logic "zero" at the output terminal and finally the condition of a "zero" at one input and a "one" at the other input produces a "zero" at the output.

Abstract: A method for removing projections from the surface of epitaxially-deposited semiconductor layers is described. These projections can adversely affect the results of photolithographic processing. The method comprises forming an oxide layer on the surface and mechanically fracturing the oxide-coated projections. In the ensuing step anisotropic semiconductor etchants are applied to the surface to remove the projections selectively.

Abstract: Semiconductor wafer handling apparatus comprising a wafer feed machine, a dispensing adapter, and a collecting adapter is disclosed. The wafer feed machine is adapted for the transfer of a plurality of semiconductor wafers from or to a wafer cassette and to dispense or collect wafers singly, in a horizontal disposition to or from a work surface. The wafer feed machine comprises a frame-like support member in which are rotatably mounted a plurality of feed screw means which are axially parallel and spaced apart so as to accept in the periphery of the screw threads a standard semiconductor wafer. The pitch of the screw threads matches the spacing of standard wafer cassettes to enable batch transfer of wafers to and from the side of the wafer feed machine. Common drive means are provided for rotating the screw feed means which produces axial movement of the wafers.

Abstract: In a vacuum system for subjecting a workpiece such as a semiconductor wafer to a beam of energy, for example as in cathodic sputtering, temperature rise of the workpiece is inhibited by mounting the workpiece in minimal thermal contact with the support structure, and orienting it so that the back surface of the workpiece, that is, the face opposite to that upon which the energy beam impinges, is directed to a black body or low temperature portion of the vacuum chamber. In combination with this technique, the back surface is suitably treated to increase its emissivity such as, for example, by applying thereto a black coating.

Abstract: An hermetic sealed microwave diode package having high thermal conductivity and very low parasitic impedances. The diode chip is mounted upon a diamond member embedded in a copper base member so that the diamond mounting surface and the copper base member surface are coplanar. A fused silica insulator ring produced by selective grit blasting surrounds the chip and is mounted likewise entirely on the diamond surface. The silica insulator has a height comparable to the thickness of the semiconductor chip and the enclosure is completed by a metal covering member which includes a contact to the top surface of the diode chip. The package thereby has extremely short conductive paths and low capacitance by virtue of the very small silica insulator ring.

Abstract: Plastic encapsulation in the form of a thin film of silicone resin is provided on the active surface of beam lead semiconductor chips by a multistep process. An etchable organic film, for example, of silicone resin, is applied to the chips while they are still in wafer form. A mask is formed on top of the resin having a pattern conforming to the underlying semiconductor chips. The exposed resin overlying the intervening beam lead grid portion is then dissolved, after which the mask is removed. The final step is the standard wafer separation which leaves each semiconductor chip with a thin silicone resin coating over the active surface thereof.

Abstract: During the removal of material selectively, by the sputter etching of the surface of a semiconductor wafer, the wafer is moved so as to produce a continuously varying angle of incidence between the ion beam and the wafer surface. There is also provided a field-free region adjoining the surface of the wafer which is being etched. As a consequence, the sputtering beam strikes the wafer surface over a range of angles which results in more complete removal of material, particularly material overlying stepped portions of the surface.

Abstract: An attenuating member comprising a plurality of passages like a tube nest, is positioned between the electrodes of a diode sputter-etching system and close or next to the anode. The passages of the attenuating member are parallel to the direct path between the electrodes and have a length appreciably greater than their maximum width. A bias on the attenuating member tends to cause secondary electrons emitted by ion bombardment at the cathode to pass through the attenuating member with a minimum of collisions. Upon striking the anode, X-rays generated at the anode by the collision of the secondary electrons are inhibited from traveling back to the workpiece by the interposition of the attenuating member. The arrangement is important in the fabrication of surface-sensitive devices such as MOS devices in which the impingement of even low energy X-rays may affect critical operating parameters, in particular, the threshold voltage.