Abstract: A single-poly non-volatile memory includes a PMOS select transistor (210) formed with a select gate (212), and P+ source and drain regions (211, 213) formed in a shared n-well region (240), a serially connected PMOS floating gate transistor (220) formed with part of a p-type floating gate layer (222) and P+ source and drain regions (221, 223) formed in the shared n-well region (240), and a coupling capacitor (230) formed over a p-well region (250) and connected to the PMOS floating gate transistor (220), where the coupling capacitor (230) includes a first capacitor plate formed with a second part of the p-type floating gate layer (222) and an underlying portion of the p-well region (250).

Abstract: A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist which includes resist openings formed over the active circuit areas as well as additional resist openings formed over inactive areas in order to maintain the threshold coverage level to control the amount of resist coverage over a semiconductor structure so that the total amount of resist coverage is at or below a threshold coverage level. Where additional resist openings are required in order to maintain the threshold coverage level, these openings may be used to create additional charge dissipation structures for use in manufacturing the final structure.

Abstract: A power control system includes a current sense resistor located on an output side of a switching power converter. By locating the current sense resistor on the output side of the switching power converter, the current sense resistor conducts a sense current when a control switch of the switching power converter is nonconductive. Since a duty cycle of the control switch is larger for a low input voltage than for a higher input voltage, the current sense resistor conducts current for a shorter time duration for low input voltages than for higher input voltages. Thus, the root mean square (RMS) of a sense current in the current sense resistor and, thus, power dissipation by the current sense resistor, is lower during low input voltages than power dissipation in conventionally located current sense resistors. The RMS of the sense current is approximately constant across a full range of input voltages.

Abstract: An apparatus and method is disclosed for providing an extensible information handling system (IHS) bus implemented on predetermined channels of a digital video interface. IHS video signal information is multiplexed with IHS bus information by a host multiplexer for transmission across a digital video connector. The multiplexed IHS video signal and IHS bus information is received by a display multiplexer, where it is demultiplexed. Demultiplexed IHS video signal information is received by a video interface receiver, where it is used to generate an image on a digital display. Demultiplexed IHS bus information is received by a host bus interface transmitter/receiver, where it is used to support peripheral devices attached to the digital display.

Abstract: A client generates a session key and a delegation ticket containing information for a requested delegation operation. The client generates a first copy of the session key and encrypts it using a public key of a proxy. The client generates a second copy of the session key and encrypts it using a public key of a server. The client then puts the encrypted session keys and delegation ticket into a first message that is sent to the proxy. The proxy extracts and decrypts its copy of the session key from the first message. The proxy then encrypts a proof-of-delegation data item with the session key and places it and the delegation ticket along with the encrypted copy of the session key for the server into a second message, which is sent to the server. The server extracts and decrypts its copy of the session key from the second message and uses the session key to obtain the proof-of-delegation data. Authority is successfully delegated to the proxy only if the server can verify the proof-of-delegation data.

Abstract: An SRAM bitcell architecture is described having a dedicated read port (N0/N1/N6, N3/N4/N7) with pull up transistors (N6, N7) that shares at least a first bit line pair (23, 24) and word line signal (25), thereby providing separate data access read paths to a 6T SRAM architecture such that the read port is connected to drive the cell read node without exposing the memory cell during read operations and to act as a write port during write operations.

Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.

Abstract: A method for enterprise application integration that uses “connectors” that can be instantiated via downloading (e.g., using Java® or other such technologies) to provide interfaces to respective disparate database systems. The databases systems may comprise any variety of now or heretofore known systems, e.g. SAP, Oracle, and so forth. The connectors can, for example, translate between a native language (or API) of the respective database systems and an internal language/protocol of the enterprise application integration system. To this end, the connectors can utilize a scripting language to access the respective database systems. Data retrieved from the database systems can be stored in a central data store in the form of RDF triplets, from which directed graphs can be generated for to generate presentations consolidated from the multiple database systems.

Abstract: A method and apparatus for testing the functionality of a circuit design uses working system data that is recorded in real-time to stimulate and/or verify a software simulation of the circuit design that does not run in real-time. In a selected embodiment, a system for simulating and verifying a software model of a baseband module circuit design is described in connection with using real-time input and output data captured from a corresponding circuit in a reference platform. The captured real-time data may include digital baseband I/Q samples and/or extracted control data pertaining to the signal level, channel frequency, gain, output power, frequency offset, DC offset, or the like. The captured data may be regenerated for use as a stimulus for the software model of the circuit design and/or to verify the functionality of the design.

Abstract: The disclosure relates to authenticating a secondary communication channel between a client application and a server application when an authenticated primary communication channel has already been established between the client application and a resource application, on which the server application can store a generated authentication token that only privileged users including the client application user can read-access and send back to the server application by way of the secondary communication channel.

Abstract: An information handling system component contained within an information handling system housing uses the information handling system housing as at least a portion of a safety enclosure for hazardous functions of the component. A lock out device disables the hazardous function if the information handling system housing is moved relative to the component. For example, an optical disc drive laser is disabled if a Hall effect sensor in the chassis of the optical disc drive no longer senses a magnet placed in a portion of the information handling system housing used to enclose the optical disc drive. Alternatively, the component couples to the information handling system housing to enclose the hazardous function within the interior of the information handling system housing so that the component is inaccessible from the exterior of the housing.

Abstract: An arbitrary number of custom catalogs for an arbitrary number of customers can be published from a single database of seller catalog data. Custom browse hierarchies can be generated for each of the custom catalogs. The custom catalogs are subsets of the catalog database, and are generated in accordance with a set of rules that defines the scope of the content of the custom catalog. The rule sets define a series of sequential searches by which a subset of the product SKUs contained in the database are returned. A primary hierarchy is maintained that can have a scope coextensive with the primary database. Custom browse hierarchies can be pruned to render their scope approximately coextensive with each subset. The custom catalog subsets and the custom browse hierarchies are generated periodically through a virtual publication process.

Abstract: A method and apparatus are described for fabricating a low-pin-count chip package (701) including a die pad (706) for receiving an integrated circuit device and a plurality of connection leads (702) having recessed lead ends (704) at the outer peripheral region of each contact lead. After forming the package body (202) over the integrated circuit device, unplated portions (104) of the exposed bottom surface of the selectively plated lead frame are partially etched to form recessed lead ends (302) at the outer peripheral region of each contact lead, and the recessed lead ends are subsequently re-plated (402) to provide wettable recessed lead ends at the outer peripheral region of each contact lead.

Abstract: A computer-based automated testing framework tests a multimedia application (such as a Flash application running in a player module) that includes one or more Flash objects by executing test scripts in an external Java-based test module that uses proxy objects in the test module to represent the Flash objects in the player module. Correspondence between the proxy object and Flash objects is maintained by translating the first test script into a command, sending the command from the external test module to the player module, interpreting the command by accessing a lookup table at the player module, and then returning a value to the external test module in response to the command.

Abstract: In order to continually receive messages in a dual personal computer system (PC) and personal digital assistant system (PDA) computer architecture, the PC system is deactivated to conserve battery power while the PDA continues to receive messages. As PDA memory is filled with messages, messages that are synchronized and archived with the PC system are 5 deleted and space is freed for incoming messages. When new and non-synchronized messages completely fill the PDA memory array, the PC system is reactivated or the user is informed.

Abstract: A secured communication channel is established between two or more information handling systems by defining attributes for encrypting information with physical inputs made at touch devices of the information handling systems. Inputting the physical gesture at a touch device of each information handling system allows evaluation of one or more attributes at each information handling system so that the shared secret of the physical gesture form the basis for encrypted communications. The touch device includes touch screens or touch pads and the attributes include gesture speed, plural distinct gesture touch points, movement of touch points relative to each other, or other attributes that are determinable from physical gesture inputs at each information handling system.

Abstract: A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.

Abstract: Wireless communication of display information between an information handling system and display is supported by a direct connection between a graphics system of the information handling system and a transceiver of the information handling system. For example, the graphics system outputs pixel level display information through a cable directly to the transceiver. A converter on the transceiver converts the display information to network information, such as from a DisplayPort format to a PCI Express format, so the transceiver can send the display information through a wireless network, such as a personal area network, to the display. A display module located at the transceiver coordinates initiation of communication of display information from the graphics system to the display.

Abstract: A storage device, such as a hard disk drive or solid state drive, reduces energy consumption by entering a reduced power state after an inactivity time where the inactivity time is set based upon I/O commands received at the storage device. For example, where commands received at a storage device are characterized in a predetermined way in terms of read commands, such as a last received command as a read command or a ratio of read commands versus write commands, a first inactivity time is applied, while commands characterized in a predetermined way in terms of write commands have a second inactivity time applied. Using a greater inactivity time during read activities than during write activities provides improved performance with reduced power consumption.

Abstract: A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer below a trench opening, a capacitor dielectric layer and a recessed top capacitor plate that is covered by an STI region and isolated from cross talk by a sidewall dielectric layer.