Patents Represented by Attorney Hamilton & Terrile, LLP
  • Patent number: 7852017
    Abstract: A lighting source ballast utilizes switching and control technology to convert an alternating current (AC) phase modulated dimmer input voltage into an approximately constant drive current to illuminate one or more light emitting diodes (LED(s)). In at least one embodiment, the state of the drive current conforms to a phase delay of the input voltage to facilitate, for example, dimming. The phase delay of the input voltage indicates a particular dimming level. The drive current varies for different dimming levels. However, the light source ballast controls drive current so that the drive current is approximately constant for each dimming level. In at least one embodiment, the ballast emulates a resistive load and, thus, the ballast has an approximately unity power factor. The switching frequency of one or more switches can be modified to spread the spectrum of electromagnetic radiation generated by the ballast.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: December 14, 2010
    Assignee: Cirrus Logic, Inc.
    Inventor: John L. Melanson
  • Patent number: 7844844
    Abstract: A power diagnostics module running on an information handling system initiates a power down state of the information handling system upon detection of a predetermined battery charge that is sufficient to allow the information handling system to recover from the power down state and run the power diagnostics module. The power diagnostics module runs on the predetermined charge to diagnose faults associated with the power system, such as failure of an external AC adapter, and to present the faults to an end user, such as at a display, with LEDs or through a network message.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: November 30, 2010
    Assignee: Dell Products L.P.
    Inventors: Mohammed K. Hijazi, Matthew Torgerson
  • Patent number: 7844919
    Abstract: The invention provides the ability to interactively select and configure a product among a set of related products based on availability and compatibility of features and options. It does not impose an order in the selection of products, features or options; only valid selections can be made at any time. To create an electronic representation of the product information to achieve the above goal, the invention provides a framework for defining a systems by defining the components of the system using elements contained in a parts catalog and defining relationships between the components of a system. A configuration system validates a configuration using the system definition, the current state of the configuration and user input.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: November 30, 2010
    Assignee: Versata Development Group, Inc.
    Inventors: Neeraj Gupta, Venky Veeraraghavan, Ajay Agarwal
  • Patent number: 7843218
    Abstract: A multiplexed data flip-flop circuit (500) is described in which a multiplexer (510) outputs functional or scan data, a master latch (520) generates a master latch output signal at a hold time under control of a master clock signal, a slave latch (540) generates a flip flop output signal at a launch time under control of a slave clock signal, clock generation circuitry (550) generates a second clock signal that has a DC state during a functional mode and has a switching state during a scan mode, and data propagation logic circuitry (564) uses the first and second clock signals to generate the master and slave clock signals during a scan mode to delay the launch time of the slave latch with respect to the hold time of the master latch.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: November 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindraraj Ramaraju, David R. Bearden, Cody B. Croxton, Prashant U. Kenkare
  • Patent number: 7820530
    Abstract: A method for forming a body contacted SOI transistor includes forming a semiconductor layer (103) having a body contact region (120), a body access region (121), and an active region (122). An SOI transistor is formed in the active region by etching a metal gate structure (107, 108) to have a first portion (130) formed over the active region, and a second portion (131) formed over at least part of the body access region. By implanting ions (203, 301) at a non-perpendicular angle into an implant region (204, 302) in the body access region so as to encroach toward the active region and/or under the second portion of the etched metal gate structure, silicide (306) may be subsequently formed over the body contact region and the implant region, thereby reducing formation of a depletion region (308) in the body access region.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: October 26, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Byoung W. Min, Stefan Zollner, Qingqing Liang
  • Patent number: 7818753
    Abstract: A method, system, apparatus, and computer program product for processing e-commerce information are presented. A first business entity and a second business entity may transfer e-commerce agreements through an electronic marketplace. After receiving a document for an e-commerce agreement that represents a legal agreement for a commercial transaction between the first business entity and the second business entity, the first business entity retrieves dependency information about the commercial transaction from the e-commerce agreement. The first business entity then incorporates the dependency information, e.g., dates, costs, deliveries, etc., as dependency relationships within a project model that represents a project for a product or service for sale by the first business entity. The project model may comprise objects representing tasks to be performed or physical components to be processed by the first business entity.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Sebastian D. Hassinger, Margaret G. MacPhail, David B. Kumhyr
  • Patent number: 7818785
    Abstract: Enhanced network security is provided through an intermediate network device, such as a switch or router, which stores in local memory a session key created based on session parameters. Subsequent attempts to communicate information through the session require authorization at the intermediate device by verification of the session key. For example, selected parameters from a protocol data unit are extracted to form a key, such as an IP address, MAC address, VLAN ID, socket number and application fields. Network accessible memory physically located in an infrastructure device provides an alternative repository for session-based information to enhance network communication security.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: October 19, 2010
    Assignee: Dell Products L.P.
    Inventors: Robert Winter, Travis L. Hart, Jr.
  • Patent number: 7818404
    Abstract: A system employing a storage device and a host for configuration information exchange between the host and the storage device. In operation, the host manages host configuration information in a data management layer of a communication model, and communicates the host configuration information to the storage device by one or more data communication layers of the communication model. Likewise, the storage device manages storage device configuration information in the data management layer of the communication model, and communicates the storage device configuration information to the host by one or more data communication layers of the communication model.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kevin D. Butt, Jose G. Miranda Gavillan, Leonard G. Jesionowski, Yun Mou, Khanh V. Ngo
  • Patent number: 7811891
    Abstract: A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (30, 32) formed over a substrate (36), thereby forming an etched gate (33) having a vertical sidewall profile (35). By constructing the gate stack (30, 32) with a graded material composition of silicon-based layers, the composition of which is selected to counteract the etching tendencies of the predetermined sequence of patterning and etching steps, a more idealized vertical gate sidewall profile (35) may be obtained.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marius K. Orlowski, Olubunmi O. Adetutu, Phillip J. Stout
  • Patent number: 7814335
    Abstract: A system and method of selectively installing software onto a computer system which includes reading a configuration file that contains computer system information, determining an encryption key from data contained in the configuration file, and deciphering data stored on a nonvolatile storage device using the encryption key. The computer system information includes system specific information that may be used to determine whether the computer system was purchased from a particular vendor. In a Windows™ based application, the configuration file includes a BIOS/DOS file that includes computer system specific information and the encryption key is optionally stored in a registry file to provide for repeated uses of the encryption key if more than one data file are being deciphered. In another embodiment, the data file is stored on a World Wide Web page accessible over a global computer network, such as the Internet, to install and decipher encrypted data files stored on a Web server.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: October 12, 2010
    Assignee: Dell Products L.P.
    Inventors: Anil V. Rao, Wayne R. Weilnau
  • Patent number: 7813455
    Abstract: A MIMO wireless communication system and method reduces the number of recursive operations when decoding received data symbols by decoding the data symbols in pairs rather than on a per symbol basis. Decoding in pairs is facilitated by the determination that errors between selected pairs of data symbols are uncorrelated and identically distributed with a determined variance. Additionally, the system and method can order the pairs and provide decoding rules that result in an insignificant loss of performance for a wide range of signal-to-noise ratios (SNRs). Furthermore, the system and method exploit the structure of the error covariance matrix to reduce computational demands.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Jayesh H. Kotecha
  • Patent number: 7811886
    Abstract: A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device (10) by forming a select gate structure (3) on a first dielectric layer (2) over a substrate (1); forming a control gate structure (6) on a second dielectric layer (5) having embedded nanocrystals (15, 16) so that the control gate (6) is adjacent to the select gate structure (3) but separated therefrom by a gap (8); forming a floating doped region (4) in the substrate (1) below the gap (8) formed between the select gate structure and control gate structure; and forming source/drain regions (11, 12) in the substrate to define a channel region that includes the floating doped region (4).
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian A. Winstead, Taras A. Kirichenko, Konstantin V. Loiko, Ramachandran Muralidhar, Rajesh A. Rao, Sung-Taeg Kang, Ko-Min Chang, Jane Yater
  • Patent number: 7809074
    Abstract: A multi-user multiple input, multiple output (MIMO) downlink beamforming system (200) is provided to enable transmit beamforming vectors to be efficiently provided to a subset of user equipment devices (201.i), where spatial separation or zero-forcing transmit beamformers (wi) are computed at the base station (210) and used to generate precoded reference signals (216). The precoded reference signals (216) are fed forward to the user equipment devices (201.i) which apply one or more hypothesis tests (207.i, 208.i) to the precoded reference signals to extract the precoding matrix (W), including the specific transmit beamforming vector (wUE) designed for the user equipment, and this extracted information is used to generate receive beamformers (vi).
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: October 5, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jayesh H. Kotecha, Jayakrishnan C. Mundarath
  • Patent number: 7809478
    Abstract: Information handling system thermal parameters applied by a thermal manager to manage cooling are adjusted based on whether or not a thermal barrier is coupled to the information handling system. The presence of a thermal barrier allows higher operating temperatures without exposing an end user to excessive thermal energy. The thermal barrier couples to the bottom of the chassis of a portable information handling system and may provide additional features, such as additional battery power storage or an optical drive.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: October 5, 2010
    Assignee: Dell Products L.P.
    Inventors: Erick Arsene Siba, Anil Damani
  • Patent number: 7805868
    Abstract: A product badge coupled to a product, such as an information handling system, displays product information to align with a selected of plural product orientations by illuminating a first display material to present the product information in a first orientation associated with a first product orientation and a second display material to present the product information in a second orientation associated with a second product orientation. For instance, illumination by a backlight presents the product information in the first orientation by interacting with the first display material, and suspension of illumination by the backlight presents the product information in the second orientation by allowing reflective light to interact with the second display material. Selection of illumination is automatically or manually accomplished.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: October 5, 2010
    Assignee: Dell Products L.P.
    Inventors: David F. Hutchinson, Charles D. Hood, Randall T. Smith
  • Patent number: 7809950
    Abstract: Information handling system security is simplified and enhanced with user passwords configurable to restrict access to the overall system and separately to the hard disk drive. An administrative password overrides the BIOS password to allow administrative access to the information handling system. Upon creation of a hard disk drive password on a system having an administrative password, the hard disk drive password is saved to the hard disk drive and to the BIOS with access from the BIOS restricted by the administrative password. Upon entry of the administrative password at the BIOS, the hard disk drive password is automatically provided from the BIOS to the hard disk drive to allow access to the hard disk drive.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: October 5, 2010
    Assignee: Dell Products L.P.
    Inventors: John Hawk, James Dailey
  • Patent number: 7809583
    Abstract: A method for a manufacturer of an information handling system to pay royalties for software preloaded onto an information handling system which includes determining when software that is preloaded onto the information handling system is executed by a user and paying a royalty for the software when the software is executed by the user so as to make the royalty payment based upon a point of use of the software is disclosed.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: October 5, 2010
    Assignee: Dell Products L.P.
    Inventors: Mujianto Rusman, David Michael, Katherine Reichert
  • Patent number: 7803670
    Abstract: A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g., 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: September 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ted R. White, Leo Mathew, Bich-Yen Nguyen, Zhonghai Shi, Voon-Yew Thean, Mariam G. Sadaka
  • Patent number: D624911
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: October 5, 2010
    Assignee: Dell Products L.P.
    Inventors: Kun-Hung Lee, Brian Hargrove Leonard, Cecilia Sun, Jason Minehart, Justin Lyles, Michael Smith, Shih-Heng Chen
  • Patent number: D625309
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: October 12, 2010
    Assignee: Dell Products L.P.
    Inventors: Andreas R. Haase, Joshua Probst