Abstract: Bandgap type reference voltage source using an operational transimpedance amplifier. The bandgap stage is formed by a first and a second bandgap branch parallel-connected; the first bandgap branch comprises a first diode and a transistor, series-connected and forming a first output node; the second bandgap branch comprises a second diode and a second transistor series-connected and forming a second output node. The operational amplifier has inputs connected to the output nodes of the bandgap stage. An amplifier current detecting stage is connected to the outputs of the operational amplifier and supplies a current related to the current drawn by the operational amplifier. A diode current detecting stage is connected to the output of the amplifier current detecting stage and to an output of the operational amplifier and supplies a current related to the current flowing in the first diode. An output stage transforms this current into a stabilized voltage.

Abstract: Described herein is a method for storing a datum in a first and a second memory cells of a nonvolatile memory. The storage method envisages programming the first and second memory cells in a differential way, by setting a first threshold voltage in the first memory cell and a second threshold voltage different from the first threshold voltage in the second memory cell, the difference between the threshold voltages of the two memory cells representing a datum stored in the memory cells themselves.

Abstract: The integrated semiconductor device includes a first chip of semiconductor material having first, high-voltage, regions at a first high-value voltage; a second chip of semiconductor material having second high-voltage regions connected to the first voltage; and a third chip of semiconductor material arranged between the first chip and the second chip and having at least one low-voltage region at a second, low-value, voltage. A through connection region is formed in the third chip and is connected to the first and second high-voltage regions; through insulating regions surround the through connection region and insulate it from the low-voltage region.

Abstract: On a semiconductor material body housing an electronic device a peripheral region of semiconductor material and at least one pad are initially formed. The peripheral region is connected to a first terminal of the electronic device and extends on at least one peripheral portion of the semiconductor material body. The pad is insulated from the semiconductor material body and is electrically connected to a second terminal of the electronic device. The semiconductor material body is fixed to a support body formed by a blank belonging to a reel. The pad is connected by a wire to an electrode formed by the blank. Next, a connection region is formed on the peripheral region and surrounds, at least partially, the semiconductor material body and the support body. The connection region is advantageously obtained by galvanic growth.

Abstract: The voltage applied to the gate terminals of the charging transistors and charge-transfer transistors of two parallel pumping branches forming a charge pump is a boosted voltage generated internally and supplied in a crosswise manner. In particular, for driving the charge pump, first and second driving signals are generated respectively for the first and for the second pumping branch via a first and respectively a second driving circuit; the first and second driving signals are also supplied respectively to a first and to a second auxiliary charge pump to obtain respectively first and second voltage-boosted signals; and the first and second boosted voltages are respectively supplied to the second and to the first driving circuit.

Abstract: A memory cell is formed with a buffer circuit. The output of the buffer circuit is linked to the input to form a logic latch. A write-access transistor is disposed between a first node linked to a bit line and the input of the buffer circuit. A control gate of the write-access transistor is linked to a second node linked to a write word line, and a read-access transistor is disposed between the first node linked to the bit line and a third node linked to a read word line. A control gate of the read-access transistor is linked to the output of the buffer circuit.

Abstract: The memory cell is of the type with a single level of polysilicon, and comprises a sensing transistor and a select transistor. The sensing transistor comprises a control gate region with a second type of conductivity, formed in a first active region of a substrate of semiconductor material, and a floating gate region which extends transversely relative to the first active region. The control gate region of the sensing transistor is surrounded by a first well with the first type of conductivity, and in turn is surrounded, below and laterally, by a second well with the second type of conductivity, thus forming a triple-well structure. A second triple-well structure can be formed in a second active region adjacent to the first active region, and can accommodate conduction regions of the sensing transistor and of the select transistor.

Abstract: A connector installation device wherein a connector has a stationary connector element and another connector element that is movable along an engagement axis with the stationary connector element and mates therewith. An insertion cam is movable perpendicular to the engagement axis of the mating connector elements. An insertion drive mechanism is interconnected with the insertion cam and is movable along an installation axis perpendicularly to the engagement axis. A drive force applied to the insertion drive mechanism translates the insertion cam along the installation axis into contact with an insertion drive surface of the insertion cam. Pressure against the insertion drive surface translates the movable connector element along the engagement axis toward the stationary connector element.

Abstract: A device and method for initializing the state of a computer, including individual transmission lines within the computer. A signal sending circuit provides an output signal onto a transmission line. While the signal is propagated along the transmission line, a second signal is provided in series on the same transmission line. Simultaneously therewith, the value of the first signal is stored in a data storage element. Subsequent bits may be placed on the transmission line before the first bit is received at a second end of the transmission line. Each bit placed on the transmission line is stored in a respective data storage element. The value of the data in the data storage elements can be tested to determine the exact state of any transmission line in the system.

Abstract: A frequency multiplier circuit and a controlling method thereof, which measures a period of a waveform by counting cycles of a fixed frequency timing signal, and reproduces the period by adding a number of prefixed length subperiods of the fixed frequency to the cycle count, making it as equal as possible to the period, so to minimize the reproduction error.

Abstract: A mixer including a stage for inputting a voltage signal to be shifted and a shift and output stage for providing frequency-shifted signals, a biasing network of the output stage including, between a high supply and a biasing node, a constant current source in parallel with an output element of a current mirror, an input element of which receives a bias order from the input stage.

Abstract: The lateral DMOS transistor is integratable in a semiconductor power device comprising a P-type substrate and an N-type epitaxial layer. The lateral DMOS transistor comprises a source region and a drain region formed in the epitaxial layer and a body region housing the source region. Between the source region and the drain region is present an insulating region extending in depth from a top surface of the epitaxial layer as far as the substrate. The insulating region presents an interruption in a longitudinal direction defining a channeling region for a current ID flowing between the source region and the drain region of the lateral DMOS transistor.

Abstract: A bi-dimensional position sensor that can be advantageously used in the turn system controlled from the steering wheel of a vehicle. The sensor includes a permanent magnet fixed to a control lever so as to move in a plane along first and second directions and to rotate about a third direction orthogonal to the preceding ones. The permanent magnet is movable with respect to an integrated device including a first group of sensor elements arranged spaced along the first direction, a second group of sensor elements arranged spaced along the second direction and a third group of sensor elements detecting the angular position of the permanent magnet. Electronics integrated with the sensor elements generate a code associated with each position which the permanent magnet may assume and generate a control signal corresponding to the desired function.

Abstract: A high-efficiency electronic circuit generates and regulates a supply voltage and includes a charge-pump voltage multiplier which is associated with an oscillator and has an output connected to a voltage regulator in order to ultimately output said supply voltage. Advantageously, the circuit comprises a first hysteresis comparator having as inputs the regulator output and the multiplier output, and comprises a second hysteresis comparator having as inputs a reference potential and a partition of the voltage presented on the regulator output. The comparators are structurally and functionally independent of each other, and their outputs are coupled to the oscillator through a logic circuit to modulate the oscillator operation.

Abstract: The boosted switch device comprises an input terminal and an output terminal; a supply line set to a supply potential; a ground line set to a ground potential; a transistor connected between the input and output terminals; a capacitor; and a switch device connecting the capacitor between the supply line and the ground line, when the transistor is off, and between the input terminal and the control terminal of the transistor, when the transistor is on.

Abstract: A preset bend resulting in a strain relief in a flexible conductor strip that interconnects relatively displaceable first and second electrical contacts that are originally relatively oriented in first spaced apart positions and moveable to second more distantly spaced apart positions. The preset bend includes a substantially straight first leg extending substantially perpendicularly to an axis of relative motion between the first and second interconnected electrical contacts and feeding into a substantially hemi-circular- curve, which continues into a second leg extending toward the second electrical contacts in their spaced apart position.

Abstract: A device for reading from a capacitive memory cell, including a comparator of the voltage stored in the memory cell with respect to a reference value, which exhibits a high input impedance; a refreshment means distinct from the comparator, the refreshment means having a low output impedance and being controlled by the comparator to impose a refreshment voltage to the memory cell; and means for controllably connecting the refreshment means to the memory cell.

Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

Abstract: An electrical connector includes a flexible circuit substrate extending between a pair of mechanical connectors to electrically couple circuits, and a supporting member between the mechanical connectors to reduce twisting of the flexible circuit substrate. The supporting member cambered to permit the mechanical connectors to translate with respect to one another. A clamping member includes a tapered clamping surface in an undeformed, unclamped position. The clamping member bends when in a clamped position, resulting in approximately planar clamping surface. Resilient pressure pads on the clamping members bias the flexible circuit substrate to the circuit board. The pressure pads are mounted in wells in the clamping members to support a side wall of the pressure pads. Frames provide additional support to the side walls of the pressure pads. The pressure pads include a raised edge along a periphery of a contact surface of the pressure pad.