Patents Represented by Attorney Harold Levine
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Patent number: 4035666Abstract: Semiconductor charge devices are defined to effect a serial-to-parallel conversion of analogue signal information. In one aspect of the invention, a digital signal is extracted from an analogue noise environment by a shift register correlator comprising a bucket-bridge configuration of field-effect transistors in combination with gating field-effect transistors which are effective to weight the amplitude of the data in corresponding bits of the shift register. The gates of the gating transistors are selectively connected to diffused regions of transistors of the bucket-brigade delay line to effect parallel tapped outputs therefrom. The weighted signals from the gating transistors are summed at a common terminal to form the auto-correlated output.Type: GrantFiled: October 8, 1975Date of Patent: July 12, 1977Assignee: Texas Instruments IncorporatedInventors: Dean Robert Collins, Lewis T. Clairborne
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Patent number: 4035619Abstract: An analog computer for controlling the ignition system of an internal combustion engine. A continuous signal is synthesized corresponding to the ignition advance angle as a function of the engine speed of rotation and of air intake pressure. This signal is synthesized in accordance with a characteristic for the particular engine concerned. The ignition advance signal is used to control commencement of a power supply pulse to the ignition system, with respect to a reference time signal, as a function of the instantaneous speed of rotation of the engine. Preferably the duration of the power supply pulse is maintained constant regardless of engine rotation speed and ignition advance angle. The circuits described for fulfilling these functions are designed for realization as bipolar integrated circuits.Type: GrantFiled: June 9, 1975Date of Patent: July 12, 1977Assignee: Texas Instruments IncorporatedInventor: Jean M. Cholet
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Patent number: 4035662Abstract: Circuit means for eliminating the effect of excessive threshold voltages in insulated gate field effect transistor inverter-type circuits utilizes capacitor pull-up. Capacitors are selectively coupled from various phased voltage outputs of a multi-phase voltage supply to the driver-gate of various field effect transistors to provide increased voltage during voltage pulses of the phase involved. A voltage between the threshold voltage and a required minimum noise margin is thereby added to the driver-gate input signal to overcome the threshold voltage effect. This circuit means is particularly useful in dynamic circuits such as multiphase shift registers and bipolar-to-high voltage field effect transistor coupled circuits.Type: GrantFiled: May 27, 1975Date of Patent: July 12, 1977Assignee: Texas Instruments IncorporatedInventor: Chang - Kiang Kuo
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Patent number: 4034234Abstract: A switching module for a solid-state keyboard or the like comprising an actuating key manually movable between a first and a second position and a variable capacitor. The capacitor has a rigid stationary electrode and another electrode movable toward and away from the stationary electrode between a first position in which the electrodes are separated by an air gap and a second position in which the air gap is substantially eliminated for effecting a change in capacitance of the variable capacitor. The movable electrode has a rigid dielectric member secured thereto on its side toward the stationary electrode, this dielectric member having a dielectric constant substantially greater than air. The switching module further comprises a cam coupling the actuating key and the movable electrode for effecting movement of the movable electrode and the dielectric member between their first and second positions in response to movement of the actuating key between its first and second positions.Type: GrantFiled: January 10, 1975Date of Patent: July 5, 1977Assignee: Texas Instruments IncorporatedInventors: Brian C. Ehlers, Henry J. Boulanger
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Patent number: 4032180Abstract: An appliance door lock has a thermally actuable latch regulated by a voltage responsive heater arranged to close the appliance circuit only after the latch has been set, to delay unlatching of the door after interruption of the appliance operation, and to assure safe latch operation when overloading of the appliance may reduce the current available to regulate lock operation.Type: GrantFiled: August 16, 1974Date of Patent: June 28, 1977Assignee: Texas Instruments IncorporatedInventor: Walter Pohl
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Patent number: 4032071Abstract: A thermally responsive valve having dual operating temperatures comprises a main body having two openings which are connected through passages in the body to an internal operating space in the body, two dish-shaped bimetal elements disposed in spaced relation to each other within the internal operating space to divide the operating space into three sections, the bimetal elements being movable in response to variations in temperature to engage and disengage respective valve seats to close and open passages between the internal operating space and the openings, and an annular wave-shaped spring arranged between the two bimetal elements holding the elements in said spaced relation.Type: GrantFiled: May 10, 1976Date of Patent: June 28, 1977Assignee: Texas Instruments IncorporatedInventor: Kazuo Imoto
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Patent number: 4031474Abstract: The specification discloses various embodiments of solid state television channel selection systems. The systems provide sequential and/or parallel access of television channels by operation of simple pushbutton or sense touch switches on the control panel of the television set, as well as sequential or parallel access of the channels through operation of remote control units. The selected television channel may be displayed in the parallel access mode by illuminating the actuated parallel access switch, or by the utilization of seven segment numerical displays with either the sequential or parallel access modes. The system enables selected television channels to be skipped during the sequential access mode. The system enables the operator to selectively choose which VHF and UHF channels may be selected by the system.Type: GrantFiled: April 7, 1976Date of Patent: June 21, 1977Assignee: Texas Instruments IncorporatedInventors: George John Ehni, III, Horst Leuschner
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Patent number: 4031415Abstract: Disclosed is an address buffer circuit for use in semiconductor memories or the like which are implemented in MOS integrated circuits. A cross-coupled differential pair of MOS transistors is used to detect an address input during a short time window, and internal address signals are generated from the state of the cross-coupled pair.Type: GrantFiled: October 22, 1975Date of Patent: June 21, 1977Assignee: Texas Instruments IncorporatedInventors: Donald J. Redwine, Norishisa Kitagawa
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Patent number: 4028907Abstract: An adjustable Joule-Thomson cryogenic cooler with a downstream thermal compensation mechanism is taught. The cryogenic cooler includes a cryogen source coupled to a manifold input port, the manifold input port connected to a heat exchanger, the heat exchanger coupled to an orifice block, and the orifice block connected to an expansion chamber. A thin cylindrical tube is attached to the manifold to support the heat exchanger. The expansion chamber is defined by the orifice block, the exterior surface of the cylindrical tube, a portion of the interior of the cylindrical tube in communication with the exterior surface of the cylindrical tube through passages, a dewar stem, and a portion of the manifold. The dewar stem encloses the cylindrical tube and sealingly engages the manifold. The thermal compensation mechanism includes a bimetal cantilever in the expansion chamber portion of the cylindrical tube, an adjustment mechanism for adjusting the effective bimetal cantilever, and a needle valve mechanism.Type: GrantFiled: December 15, 1975Date of Patent: June 14, 1977Assignee: Texas Instruments IncorporatedInventors: Rodney E. Herrington, Carol O. Taylor
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Patent number: 4030080Abstract: A variable module memory, particularly suitable for use in a programmable controller, includes a set of up-to-N memory modules each for storing a plurality of words of n bits. N receptacle means are provided for receiving the set of memory modules and for coupling the received memory modules to a common serial bus. Control means is provided, coupled via said receptacle means, to said up-to-N memory modules for providing address signals for selectively addressing the words of a selected memory module to provide the contents stored therein serially to said common serial bus. A pull-up resistor connecting a predetermined voltage to a common serial bus detects the absence of memory modules in the receptacles and forces the serial bus to a predetermined binary state for all bits or all words for a vacant receptacle means.Type: GrantFiled: December 24, 1975Date of Patent: June 14, 1977Assignee: Texas Instruments IncorporatedInventors: Bobby G. Burkett, Raymond W. Henry
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Patent number: 4030049Abstract: The specification discloses a low noise parametric amplifier for use with a radar receiver. A Gunn diode oscillator is provided to generate a pump frequency. A bandpass filter filters the pump frequency and applies the pump power through a waveguide having a reduced height portion employing a multisection Chebycheff transformer. A coaxial signal input line connects through the waveguide to a coaxial idler section which is provided to terminate the signal input line and to match the signal and idler frequencies. A varactor diode assembly is mounted on the center conductor of the signal input line and the idler section. A cup member is attached to the diode assembly for matching the parallel resonance of the diode assembly to the pump frequency.Type: GrantFiled: November 5, 1974Date of Patent: June 14, 1977Assignee: Texas Instruments IncorporatedInventors: David N. McQuiddy, Jr., Truman G. Blocker, III
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Patent number: 4029962Abstract: This disclosure defines an infrared image detector formed in a block of semiconductor material by etching slots in the semiconductor material. The slots define the individual detectors, effectively isolate them from each other both optically and electrically, and permit the detectors to be placed very close to each other. Biasing slots are etched in each detector and on two opposing sides of the detector and the walls of the slots are made highly conductive by an impurity diffusion or coating or alternatively the slots is filled with a conducting material. The conducting layer or material in each slot is connected to a conductor on the surface of the semiconductor wafer so that the conductor inside the biasing slot serves as an electrical contact for the detector. The detectors are biased electrically by applying a voltage difference between two different sets of conducting slots.Type: GrantFiled: June 23, 1975Date of Patent: June 14, 1977Assignee: Texas Instruments IncorporatedInventor: Richard Alexander Chapman
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Patent number: 4028064Abstract: A process for plating beryllium copper with an excellent electrically conductive material such as gold for use in high reliability applications wherein a heat treating step is employed after forming to yield a desired hardness spring temper comprising the steps of: providing a copper-rich surface on the beryllium copper; electroplating the copper-rich surface with a diffusion barrier preplate; heat treating the beryllium copper material to a desired temper; and electroplating the material with a high electrically conductive material. This process provides for a void-free, durable gold plate which can be produced by a continuous automated strip plating line before and after heat treating.Type: GrantFiled: February 17, 1976Date of Patent: June 7, 1977Assignee: Texas Instruments IncorporatedInventors: Stephen Cassidy, Robert Baboian, Raymond A. Frechette, Gardner S. Haynes, John W. Ross
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Patent number: 4027381Abstract: Processes for manufacturing two-phase charge coupled devices (CCDs) having marginally overlapping phase electrodes and utilizing a single insulating material. Offset self-alignment techniques are used to achieve accurate location of ion implanted potential well or potential barrier regions to achieve the required asymmetry of potential wells (or threshold voltages) in each gate region of the CCD with small bit or charge storage element sizes leading to structures having a high packing density. Fabrication of surface and buried channel structures is described.Type: GrantFiled: June 1, 1976Date of Patent: June 7, 1977Assignee: Texas Instruments IncorporatedInventors: Al F. Tasch, Jr., Robert C. Frye
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Patent number: 4027686Abstract: Method and apparatus for cleaning the surface of a slice of semiconductor material through the use of a liquid spray, wherein the liquid spray is delivered at an angle to the exposed surface of a rotating semiconductor slice at a controlled pressure and velocity, and strikes the surface of the semiconductor slice substantially along a linear path coinciding with the diameter of the slice. The apparatus includes an upstanding pedestal having a slice-supporting surface on which the slice of semiconductor material to be cleaned is disposed. The pedestal is mounted within a housing which includes a motor for imparting rotation to the pedestal and a vacuum pump for inducing a suction in openings provided in the slice-supporting surface of the pedestal so as to retain the slice in place when rotary movement is imparted thereto.Type: GrantFiled: January 2, 1973Date of Patent: June 7, 1977Assignee: Texas Instruments IncorporatedInventors: Samuel R. Shortes, Edwin Graham Millis
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Patent number: 4028561Abstract: A completely integrated npn Darlington stage is provided using an n-type film deposited on an n+ substrate. A p-type boron base is first partially diffused into the n layer, then an oxide window is cut into the oxide formed during the base diffusion, in the area designated for the speedup transistor. A high temperature boron deposition is performed in the oxide window, and the base diffusion completed. The times of the base diffusion steps are chosen so that the penetration of the more lightly doped region slightly exceeds that of the heavily doped region. Oxide windows are then cut for the driver, output and speedup device emitters and the emitter diffusion performed in standard manner. Fabrication is completed using normal single diffused techniques. The effect of the heavy doping of the base region of the speedup transistor is to create a very low gain transistor which has a BV.sub.CEO nearly equal to the BV.sub.CEX rating.Type: GrantFiled: March 23, 1976Date of Patent: June 7, 1977Assignee: Texas Instruments IncorporatedInventors: Christopher T. Black, Anthony Lear
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Patent number: 4028715Abstract: It is frequently desirable to establish the level of charge in the first potential well of a CCD in accordance with an external electrical signal. Thermal noise associated with the output resistance of the external source gives rise to uncertainty in this charge level. The use of a floating diffused region as an intermediate receptacle for the charge introduced permits a substantial reduction in the magnitude of this uncertainty.Type: GrantFiled: September 30, 1975Date of Patent: June 7, 1977Assignee: Texas Instruments IncorporatedInventor: Stephen P. Emmons
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Patent number: 4027382Abstract: Process for manufacturing two-phase charge coupled devices (CCDs) having marginally overlapping phase electrodes and utilizing a single insulating material. Offset self-alignment techniques are used to achieve accurate location of ion implanted potential well or potential barrier regions to achieve the required asymmetry of potential wells (or threshold voltages) in each gate region of the CCD with small bit or charge storage element sizes leading to structures having a high packing density. Fabrication of surface and buried channel structures is described.Type: GrantFiled: June 1, 1976Date of Patent: June 7, 1977Assignee: Texas Instruments IncorporatedInventors: Al F. Tasch, Jr., Robert C. Frye
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Patent number: 4028648Abstract: A tunable surface wave resonator is disclosed comprising a substrate of piezoelectric material having acoustic surface wave absorbing extremities, a pair of spaced acoustic surface wave gradient reflectors positioned adjacent to the absorbing extremities of the substrate, a pair of spaced multiphase surface wave tuning transducers selectively positioned between the pair of gradient reflectors over antinode positions of desired resonant frequency standing wave, and an acoustic surface wave transducer selectively placed for optimum coupling of energy into the acoustic resonant cavity formed by the pair of gradient reflectors.Type: GrantFiled: March 8, 1976Date of Patent: June 7, 1977Assignee: Texas Instruments IncorporatedInventors: Clinton S. Hartmann, Robert E. Stigall
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Patent number: D244761Type: GrantFiled: September 11, 1975Date of Patent: June 21, 1977Inventor: Eugene Joseph Sulek