Patents Represented by Attorney, Agent or Law Firm Hayes, Soloway, Hennessey, Grossman & Hages PC
  • Patent number: 6735704
    Abstract: A power management system and method for multiple redundant power supplies. The present invention provides management and control of N+M power supplies, where N represents the minimum number of power supplies required and where M is the number of redundant power supplies (M>1), where any one of the power supplies may be capable of supplying power to all the loads of the power subsystems. In the preferred embodiment each power subsystem includes a power supply and a controller coupled to a power bus. A communication bus is provided common to each power subsystem. During reset or power-on periods, the controllers are programmed to uniquely delay the start time of each power supply, thereby protecting against an overcurrent/overvoltage condition on the power bus during reset periods. A master controller is provided to monitor normal operating conditions of the power subsystems and communication bus.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: May 11, 2004
    Assignee: International Business Machines Corporation
    Inventors: David Butka, Brian Gerard Goodman, Leonard George Jesionowski, Michael Philip McIntosh, Robin Daniel Roberts, Raymond Yardy
  • Patent number: 6426523
    Abstract: Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3+SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower rising voltage and higher breakdown characteristics is obtained.
    Type: Grant
    Filed: October 27, 1997
    Date of Patent: July 30, 2002
    Assignee: NEC Corporation
    Inventors: Keiko Yamaguchi, Naotaka Iwata
  • Patent number: 6389669
    Abstract: An apparatus and method for extracting a doctor blade from paper making machines including a clamping and locking mechanism that tightens as more force is applied to the device in the extraction process. The apparatus may include a hollow steel handle or outer shaft, a locking linkage shaft slidably disposed within the steel outer shaft, and a rotatably mounted gripping mechanism coupled to the linkage. A trigger mechanism attached to the linkage shaft causes the gripping mechanism to rotate against the doctor blade, gripping the blade between contact surfaces. A safety locking ring may be provided for securing the linkage shaft in a closed position. As force is applied against the extractor, the gripping action is increased by the frictional action exerted by the gripping mechanism on the doctor blade.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: May 21, 2002
    Inventor: John Moscone
  • Patent number: 6376920
    Abstract: A semiconductor chip has a first ground line for maintaining a stable ground potential for the internal circuit. The first ground line is connected to a second ground line disposed on a scribe region of the semiconductor chip via a bonding pad, which is connected to an external lead frame. I/O circuit has a third ground line directly connected to the second ground line without passing the bonding pad. The noise propagated from the third ground line to the first ground line is reduced by passing the noise through the bonding pad.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: April 23, 2002
    Assignee: NEC Corporation
    Inventors: Kayoko Ikegami, Takuya Hirota
  • Patent number: 6371548
    Abstract: A vehicle interior trim panel and method of making is provided where the vehicle interior trim panel comprises a skin, a substrate, a foam located between the skin and the substrate, and a flat wire at least partially surrounded by and embedded in the foam.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: April 16, 2002
    Assignee: Textron Automotive Company Inc.
    Inventor: David Mark Misaras
  • Patent number: 6363581
    Abstract: A hose clamp is provided for establishing a reliable, fluid-tight, seal between a hose and a receptacle therefore or to another length of hose. The clamp includes a plurality of clamp segments and a span ring, e.g., a spiral wound ring. Each clamp segment includes an arcuate interior surface having a span ring slot therein which is positioned to align with a corresponding span ring slot in an adjacent clamp segment. The span ring has a portion disposed in each span ring slot with the interior surface the span ring approximately flush with the interior surfaces of the segments. Each clamp segment further includes a bore on a first end thereof which is adapted to align with a corresponding bore on an end of an adjacent segment. A fastener, e.g., a screw, may be inserted into the bores to draw the ends of the clamp segments toward each other, thereby tightening the segments of the clamp around the hose and receptacle.
    Type: Grant
    Filed: April 10, 2000
    Date of Patent: April 2, 2002
    Assignee: JGB Enterprises, Inc.
    Inventor: Guy Anthony Zipp
  • Patent number: 6354623
    Abstract: An automotive trim panel is disclosed having an airbag door and at least one duct. The trim panel comprises a first retainer, having an aperture for deployment of an airbag, and a second retainer having an airbag door. When the first retainer and the second retainer are assembled, the airbag door of the second retainer is received in the aperture of the first retainer. Furthermore, at least one duct is formed when the first retainer and the second retainer are assembled.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: March 12, 2002
    Assignee: Textron Automotive Company Inc.
    Inventor: John A. Delmastro
  • Patent number: 6337547
    Abstract: The linking component between two parts that contributes to maintaining them at a distance that is determined but adjustable comprises a jack with a screw and a nut. The movement of the jack is controlled by a motor. Universal joints are disposed between the two parts and the screw and the nut respectively, and the axes of rotation of one of the universal joints passes through the center of the nut. If play present in the assembly causes the screw to become skewed relative to the nut, the nut tilts freely until its axis is in line with that of the screw, thereby eliminating the flexion stresses caused by the cantilever on the screw. The component may be used to regulate the angle between two hinged sections of a robot arm.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: January 8, 2002
    Assignees: Commissariat a l'Energie Atomique, Compagnie Generale des Matieres Nucleaires
    Inventor: Tanguy Jouan de Kervenoaƫl
  • Patent number: 6326842
    Abstract: A variable gain amplifying apparatus which can accurately set a predetermined gain for amplifying. The variable gain amplifying apparatus has a first amplifying circuit, a second amplifying circuit and a third amplifying circuit. The first amplifying circuit can control a first gain during an operation. The second amplifying circuit is coupled to an output of the first amplifying circuit, in which a gain is fixed during an operation. The third amplifying circuit coupled to an output of the second amplifying circuit, in which a gain can be controlled during an operation. The apparatus can avoid deterioration in a distortion characteristic, an increase in a total noise figure and an increase in a consumptive electric power.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: December 4, 2001
    Assignee: NEC Corporation
    Inventor: Hidehiko Kuroda
  • Patent number: 6324156
    Abstract: A recording film has recording tracks that record information and separating regions that separate neighboring recording tracks. A recording film reflects light when performing recording, playback, and erasing of information. A protective film has a pattern of surface unevenness that corresponds with the recording racks and separating regions, and has a thickness at a recording track whereby there is a change in reflectivity of the reflective film depending upon whether or not there is information recorded, and a thickness at the separating regions such that reflectivity does not depend upon whether information is recorded.
    Type: Grant
    Filed: June 7, 1999
    Date of Patent: November 27, 2001
    Assignee: NEC Corporation
    Inventor: Yoshitaka Kawanishi
  • Patent number: 6323931
    Abstract: An interterminal anti-short-circuiting pattern is formed in an upper metal wire included in a connection terminal 3, for connecting to external driving LSI and the like, located on the projected portion of a bottom glass substrate 2. This pattern includes recess 4 and island 5 on which a contact hole 12a is formed through a protective insulating film. The protective insulating film has high residence to water penetration. Spread of the corrosion can be shut off by the recess surrounding the island. Short circuit occurrence due to interterminal current leak can be inhibited under high moisture conditions in the semiconductor device used for active matrix display, e.g. LCD panel.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: November 27, 2001
    Assignee: NEC Corporation
    Inventors: Akira Fujita, Choei Sugitani
  • Patent number: 6323136
    Abstract: A semiconductor substrate is dipped into a contaminating treatment liquid whose pH value is controlled depending on the property of metal impurities, so as to produce a sample contaminated with metal of a desired concentration. Alternatively, a semiconductor substrate is kept in a hermetic container along with desired organic matter so as to produce a sample contaminated with the organic matter in the form of vapor obtained through vapor-liquid or vapor-solid equilibrium.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: November 27, 2001
    Assignee: NEC Corporation
    Inventor: Yoshimi Shiramizu
  • Patent number: 6323109
    Abstract: An insulation film is formed on a first single crystal silicon substrate, e.g., a hydrogen anneal substrate, an intrinsic gettering substrate and an epitaxial substrate. Hydrogen implantation is carried out from a surface of this insulation film, thereby forming a hydrogen implantation region in the first single crystal silicon substrate. Then, by carrying out a thermal treatment at 400 to 500° C., voids are formed in the hydrogen implantation region, and the first single crystal silicon substrate is cleaved therefrom. Next, the surface of the insulation film and a surface of a second single crystal silicon substrate are laminated and then, they are subjected to a thermal treatment at 1,000° C. or higher. With this method, the adverse influence, on a device, of defects in the substrate can be reduced and a yield can be enhanced.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: November 27, 2001
    Assignee: NEC Corporation
    Inventor: Kensuke Okonogi
  • Patent number: 6320741
    Abstract: The present invention provides a electrical double layer capacitor that can prevent the leakage of an electrolyte solution to the outside that is caused by the fractures occurring in the collectors, and thereby both the yield during manufacture processing and the reliability can be improved. Chamfered portions 20 are formed on the corners that are the border between components that are adjacent to the surfaces 12a and 12a of the polarizing electrodes 12 that do not contact a separator 11 and a collector 13, and thereby, the stress focus on these corners, which occurs easily at the contacting portions between the polarizing electrode 12 and the collector 13, occurs with difficulty.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: November 20, 2001
    Assignee: NEC Corporation
    Inventors: Masako Ohya, Satoshi Arai
  • Patent number: 6320420
    Abstract: A dynamic logic element and a dynamic logic circuit realized by using such dynamic logic elements which is not affected by a clock skew and is capable of operating at high speed. The dynamic logic element comprises a detecting circuit portion which receives an output signal of the dynamic logic element fed back thereto, which detects completion of a precharge operation, and which, upon detection of completion of a precharge operation, autonomously finishes a precharge phase and starts an evaluation phase. A plurality of the dynamic logic elements are coupled in tandem to form a domino logic circuit. A plurality of the domino logic circuits are coupled in tandem without interposing a buffer circuit therebetween to realize a high speed dynamic logic circuit.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: November 20, 2001
    Assignee: NEC Corporation
    Inventor: Atsufumi Shibayama
  • Patent number: 6320376
    Abstract: A magnetic field sensor has a first conductor, a first insulating film, a second conductor, a second insulating film and a third conductor. The first conductor is composed of a “C-shaped” portion, which is formed in a C-like shape, and a linear portion, which is connected to one side of the “C-shaped” portion which is opposite to a gap of the “C-shaped” portion. The first insulating film is formed on the first conductor and has a hole in a predetermined position. The second conductor is formed in a ladle-like shape, and is formed on the first insulating film such that its one side corresponding to the front end of the ladle overlaps with a straight line, through which an outer edge of one end and an outer edge of the other end of the “C-shaped” portion.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: November 20, 2001
    Assignee: NEC Corporation
    Inventors: Naoya Tamaki, Norio Masuda, Masahiro Yamaguchi, Ken-Ichi Arai
  • Patent number: 6319797
    Abstract: An HSQ film 4 is formed on a silicon oxide film 1 and the film 4 is subject to B2H6 plasma irradiation, to form a boron-implanted region 5. After forming a plasma TEOS film 6 on the region, a concave 8 is formed with a hydrofluoric acid-containing etchant, while wet-etching is stopped on the boron-implanted region 5. Then, the exposed HSQ film 4 in the bottom of the concave 8 is dry-etched to form a contact hole 9 reaching an Al interconnection 2. Then, the contact hole 9 is filled with an upper interconnection material to provide a multilayered interconnection structure.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: November 20, 2001
    Assignee: NEC Corporation
    Inventor: Tatsuya Usami
  • Patent number: 6316816
    Abstract: The disclosure relates to the contacts of a polysilicon resistor for semiconductor integrated circuits. The polysilicon resistor has a resistor pattern of a doped polysilicon film formed on a first dielectric film on a semiconductor substrate. The first dielectric film and the polysilicon resistor pattern are overlaid with a second dielectric film. Each contact window for the polysilicon resistor pattern is opened in the second dielectric film and the polysilicon resistor pattern so as to reach the upper surface of the first dielectric film. It is preferable that the contact windows intrudes into the first dielectric film. As a result, side surfaces of the polysilicon film are exposed in each contact window. The contact windows are filled with a contact metal. The etching process for forming the contact windows does not affect the thickness of the polysilicon film, and only side surfaces of the polysilicon film make contact with the contact metal.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: November 13, 2001
    Assignee: NEC Corporation
    Inventor: Naoya Matsumoto
  • Patent number: 6316328
    Abstract: A fabrication method for a semiconductor device is provided, which is able to increase pattern-to pattern lithography overlay accuracy. After a first layer made of a first material is formed, first and second slits serving as a first alignment mark are formed in the first layer. The first and second slits are spaced with a specific distance and are approximately parallel to each other. Each of the first and second slits is filled with a second material. Then, a second layer made of a third material is formed on the first layer. Subsequently, a mask is formed on the second layer. The mask has a first pattern serving as a second alignment mark. The second alignment mark is overlapped with the first and second slits serving as the first alignment mark. Preferably, the first alignment mark provides the main scale of a caliper, and the second alignment mark provides the vernier scale of the caliper.
    Type: Grant
    Filed: March 10, 1999
    Date of Patent: November 13, 2001
    Assignee: NEC Corporation
    Inventor: Masahiro Komuro
  • Patent number: 6315819
    Abstract: There is provided a method of dry etching a nickel film formed on a substrate by means of plasma of an etching gas, wherein the etching gas includes at least one of CO and CO2 gases, and the substrate is designed to keep a temperature in the range of −25° C. to 40° C. both inclusive, while the substrate is being etched. For instance, the etching gas is a mixture gas including CO and CO2 gases, a mixture gas including CO, CO2 and H2 gases, or a mixture gas including CO and H2 gases. The above-mentioned method provides higher etching accuracy, higher etching rate, and less etching damage in a substrate.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: November 13, 2001
    Assignee: NEC Corporation
    Inventor: Masatoshi Tokushima