Patents Represented by Attorney Hayes Soloway
  • Patent number: 5654585
    Abstract: There is provided a semiconductor device and a lead frame in which the cross section of bent portions (5a, 5b) of a gull wing type external lead (3) having a plurality of bent portions (5a, 5b) is arranged so that the width of bended inside is formed wider than that of the outside. By forming the external lead (3) in this manner, the external lead (3) of the lead frame is stably formed, and when the semiconductor device is mounted on a printed circuit board (9), a solder fillet is sufficiently formed about the bent portion (5b), and the connecting reliability can be made increased.
    Type: Grant
    Filed: September 20, 1995
    Date of Patent: August 5, 1997
    Assignee: NEC Corporation
    Inventor: Hideyuki Nishikawa
  • Patent number: 5653549
    Abstract: An unlockable connecting device between two objects is provided. The device includes a connecting member for connecting the objects when the device is in a connected state, and an elastic system for applying to the connecting member a tensile stress for breaking the connecting member when the device is in a separation state. The tensile stress is caused by expansion of the elastic system as a result of elastic resiliency of the elastic system.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: August 5, 1997
    Assignee: Aerospatiale Societe Nationale Industrielle
    Inventors: Freddy Geyer, Gerard Vezain
  • Patent number: 5653893
    Abstract: Through-holes are formed in a printed circuit board substrate by chemical etching a metal foil clad circuit board having open positions in the metal foil where a hole is to be formed using N-methyl-2-pyrrolidone, a mixture of methylene chloride and HF, or a mixture of methylene chloride, HF and xylene.
    Type: Grant
    Filed: June 23, 1995
    Date of Patent: August 5, 1997
    Inventor: N. Edward Berg
  • Patent number: 5655034
    Abstract: A Mach-Zehnder modulator has a first waveguide path, a second waveguide path and first and second phase modulator sections respectively formed in the first and second waveguide paths. Those two waveguide paths have different equivalent refractive indexes so that with no modulation electric signal applied to the first and second phase modulator sections, lights waveguided through the first and second phase modulator sections have a phase difference of (2N+1).pi. (N: 0 or a positive integer). No voltage or a constant voltage is applied to the second phase modulator section, and a modulation signal is applied to the electrode of the first phase modulator section. When a voltage of 0 is applied to the first phase modulator section, a light OFF state is acquired, and when a voltage of V.pi. is applied to the first phase modulator section, a light ON state is acquired. Therefore, negative chirping is generated at the light ON time and the light OFF time.
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: August 5, 1997
    Assignee: NEC Corporation
    Inventors: Masashige Ishizaka, Junichi Shimizu
  • Patent number: 5652452
    Abstract: A semiconductor device has a structure in which pluralities of gate electrodes, drain electrodes, and source electrodes extend in parallel to each another. The semiconductor device includes at least one isolation area formed in a direction perpendicular to at least one gate electrode so as to separate one active layer area formed on a semiconductor substrate into a plurality of active layer areas. The at least one gate electrode is connected to each of the plurality of active layer areas separated by the at least one isolation area.
    Type: Grant
    Filed: February 2, 1996
    Date of Patent: July 29, 1997
    Assignee: NEC Corporation
    Inventor: Kazunori Asano
  • Patent number: 5652159
    Abstract: In a method of manufacturing a thin film transistor, a light shielding gate electrode is formed on a transparent insulating substrate. On the substrate including the gate electrode are laminated a gate insulating film, a semiconductor film, a protection insulating film, and a photoresist film. The photoresist film is patterned in alignment with the gate electrode. The protection insulating film is isotropically etched using the patterned photoresist film as a mask to have inclined portions. After the surface of the semiconductor film is rinsed to remove a natural oxide film, a metal film is deposited to form a metal silicide layer in alignment with the patterned protection insulating film. The metal film is patterned in such a manner that the metal portions are separated from the patterned protection insulating film.
    Type: Grant
    Filed: October 26, 1995
    Date of Patent: July 29, 1997
    Assignee: NEC Corporation
    Inventor: Naoto Hirano
  • Patent number: 5652154
    Abstract: In a method for manufacturing a "BiCMOS" semiconductor integrated circuit, a gate oxide film 110 and a polysilicon film are grown on a semiconductor substrate, and after phosphorus is doped, the polysilicon film is patterned to form gate electrodes 112a and 112b and an emitter electrode 112c. A heat treatment is performed to form an emitter diffused region 113. Phosphorus and boron are selectively implanted with a low impurity concentration, respectively, to form a LDD N.sup.- region 114 and a LDD P.sup.- region 115. Thereafter, a side wall 116 is formed, and boron is implanted into areas B and C so as to form P.sup.+ source/drain regions 117 and a graft base region 18, respectively. Phosphorus is implanted to form N.sup.+ source/drain regions 119.
    Type: Grant
    Filed: July 8, 1996
    Date of Patent: July 29, 1997
    Assignee: NEC Corporation
    Inventor: Toshio Komuro
  • Patent number: 5650042
    Abstract: In an SOI substrate having a base substrate, an insulating film and a semiconductor active layer, a potential difference is given between the base substrate and an etching solution or among the base substrate, the semiconductor active layer and the etching solution to form a uniform depletion layer on the active layer side from the interface between the insulating film and the active layer. The semiconductor active layer is uniformly thinned down by etching using a solution or by the combination of chemical or electro-chemical surface and etching with the resultant reaction product. In this case, the individual electrodes are provided with seal members to prevent the base substrate electrode and the active layer electrode from contacting the etching solution or the reaction solution due to the etching using the etching solution or the chemical reaction using the reaction solution.
    Type: Grant
    Filed: September 27, 1995
    Date of Patent: July 22, 1997
    Assignee: NEC Corporation
    Inventor: Atsushi Ogura
  • Patent number: 5650649
    Abstract: A floating gate type field effect transistor has a floating gate electrode formed of p-type polysilicon and a control gate electrode capacitively coupled to the floating gate electrode, and an erasing pulse signal is applied to the control gate electrode so that accumulated electrons are drifted in a depletion layer formed in the floating gate electrode toward a lower insulating layer, thereby evacuating the electrons to a silicon substrate without deterioration of the lower insulating layer.
    Type: Grant
    Filed: May 16, 1996
    Date of Patent: July 22, 1997
    Assignee: NEC Corporation
    Inventor: Masaru Tsukiji
  • Patent number: 5649855
    Abstract: In a wafer polishing device, a resin sheet polishes a wafer with a polishing liquid fed thereto, while sliding on the wafer. Tension mechanisms apply an adequate degree of tension to the sheet in order to provide it with a desired elastic strength. Even if the wafer has a deformation or roughness ascribable to its uneven thickness, the sheet corrects some degree of deformation and then polishes the wafer, following the corrected configuration of the wafer. At this instant, the pressure acting on the wafer is even over the entire surface of the wafer. The sheet is formed of a material which is hydrophilic and resistant to fluoric acid. With this construction, the device corrects irregularities ascribable to the formation of a device from the wafer even if the wafer itself has any deformation or irregularity.
    Type: Grant
    Filed: January 23, 1996
    Date of Patent: July 22, 1997
    Assignee: NEC Corporation
    Inventor: Shinichi Chikaki
  • Patent number: 5650992
    Abstract: A phase change optical disk 10 is disclosed, which comprises a first dielectric layer 14, a recording layer 16, a second dielectric layer 18, a reflective layer 20, a third dielectric layer 22, and an ultraviolet cure resin layer 24, these layers being laminated in the mentioned order on a substrate 12. The substrate 12 is of polycarbonate or the like, the first to third dielectric layers 14, 18 and 22 are of ZnS-SiO.sub.2 or the like, and the recording layer 16 is of GeSbTe or the like. The reflective layer 20 is of a tarnsparent material, such as silicon (Si) or germanium (Ge).
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: July 22, 1997
    Assignee: NEC Corporation
    Inventor: Shuichi Ohkubo
  • Patent number: 5647527
    Abstract: The present invention provides a method of determining an order of wire-bonding between a plurality of leads and a plurality of electrodes, the leads being arranged in two arrays, the electrodes being disposed intermediate between the two arrays of leads in a line on a semiconductor, the method including the steps of (a) surveying whether, if a first wire for connecting a first electrode to a first lead is extended beyond the first electrode, the extended first wire would intersect with a second wire for connecting a second electrode to a second lead, and (b) carrying out wire-boding for the first wire and then wire-bonding for the second wire if the extended first wire would intersect with the second wire.
    Type: Grant
    Filed: February 5, 1996
    Date of Patent: July 15, 1997
    Assignee: NEC Corporation
    Inventor: Kenji Oyachi
  • Patent number: 5646533
    Abstract: A device for induction measurement of a medium adjacent a cylindrical, metallic, magnetic walled well of a well casing includes at least two magnetic circuits for magnetically saturating the metallic wall. Each of the magnetic circuits has a plate-like central portion, situated between two lateral portions, each of which lateral portions has a lateral end which comes into contact with the wall, along a zone parallel to the cylindrical axis of the wall. After magnetic saturation of the metallic wall, an induction signal is induced into the medium beyond the metallic wall and retransmitted by the medium in response to the induction signal.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: July 8, 1997
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Marcel Locatelli, Jean-Jacques Chaillout, Michel Brochier
  • Patent number: 5643422
    Abstract: A titanium nitride layer is deposited on a semiconductor substrate through a magnetron sputtering using a titanium target, and the sputtered surface is mainly formed by (001) crystal surfaces, at least 90 percent of which have respective <001> directions falling within 30 degrees with respect to a normal line to the a major surface of the semiconductor substrate, thereby preventing the sputtered surface from nitriding.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: July 1, 1997
    Assignee: NEC Corporation
    Inventor: Yoshiaki Yamada
  • Patent number: 5643802
    Abstract: A method of producing a semiconductor device is disclosed and includes steps of temporarily connecting inner leads or lands provided on a film carrier tape and electrode pads provided on an IC chip at the same time by low-temperature gang bonding, and then bonding them by point bonding. The method enhances the reliable production of a semiconductor device by reducing the influence of localized load and temperature ascribable to the short accuracy of the gang bonding jig as well as the influence of the deformation of a film carrier tape due to heat applied during point bonding.
    Type: Grant
    Filed: April 18, 1996
    Date of Patent: July 1, 1997
    Assignee: NEC Corporation
    Inventor: Chikara Yamashita
  • Patent number: 5644535
    Abstract: A memory access request signal is generated with activation of three different signals, i.e., memory select signal, operating mode signal and operating input signal. When only the memory select signal and operating mode signal are activated, internal operation is not executed, and only an operating mode for determining access allow signal generation timing is determined. The access allow signal is generated at the same timing as the execution of the operating mode.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: July 1, 1997
    Assignee: NEC Corporation
    Inventor: Tamio Shimizu
  • Patent number: 5642315
    Abstract: A static type of semiconductor memory device includes a power supply line for supplying a power supply voltage, a pair of bit lines, a word line, and a memory cell connected to the word line and the pair of bit lines. The power supply voltage is boosted up to provide the boosted voltage on a boosted voltage line. A predetermined voltage is supplied to the word line using the boosted voltage and a write operation or read operation is performed to the memory cell via the pair of bit lines when the predetermined voltage is supplied on the word line. The predetermined voltage is approximately equal to a sum of the power supply voltage and a threshold voltage of a MOS transistor, resulting in a great low voltage operation margin.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: June 24, 1997
    Assignee: NEC Corporation
    Inventor: Takashi Yamaguchi
  • Patent number: 5639517
    Abstract: A method is provided for fabricating thin films having various optical properties is provided. The disclosed method includes preparing a colloidal suspension and depositing the suspension on a substrate using a coating cylinder. The disclosed method finds particular utility in the area of manufacturing dielectric mirrors and non-reflecting films.
    Type: Grant
    Filed: January 9, 1995
    Date of Patent: June 17, 1997
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Herve Floch, Philippe Belleville
  • Patent number: 5640097
    Abstract: A test pattern for contact resistance, includes a contact hole section, and first to fourth electrode pad patterns connected to the contact hole section.
    Type: Grant
    Filed: October 1, 1996
    Date of Patent: June 17, 1997
    Assignee: NEC Corporation
    Inventor: Hiromitsu Hada
  • Patent number: D380582
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: July 1, 1997
    Assignee: Vigilant Incorporated
    Inventor: Gregory M. Filias