Abstract: An implantable vascular prosthesis is provided for use in a wide range of applications wherein at least first and second helical sections having alternating directions of rotation are coupled to one another. The prosthesis is configured to conform to a vessel wall without substantially remodeling the vessel, and permits accurate deployment in a vessel without shifting or foreshortening.

Abstract: This application relates to decoding signals that carry clock and data information. In particular, it relates to construction a time-varying histogram of inter-arrival times between pulse edges and using the histogram to identify whether a pulse edge encodes a single length interval, a double length interval or some longer length interval. Further details and embodiments of the technology disclosed are provided in the drawings, detailed description and claims.

Abstract: The current invention relates to writing or reading a pattern on a surface, such as in microlithography or inspection of mircrolithographic patterns. In particular, Applicant discloses systems recording or reading images by scanning sparse 2D point arrays or grids across the surface, e.g., multiple optical, electron or particle beams modulated in parallel. The scanning and repeated reading or writing creates a dense pixel or spot grid on the workpiece. The grid may be created by various arrays: arrays of light sources, e.g., laser or LED arrays, by lenslet arrays where each lenslet has its own modulator, by aperture plates for particle beams, or arrays of near-field emitters or mechanical probes. For reading systems, the point grid may be created by a sparse point matrix illumination and/or a detector array where each detector element sees only one spot. The idea behind the use of large arrays is to improve throughput.

Abstract: Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.

Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.

Abstract: A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.

Abstract: An electrode structure including two parallel electrical paths. A plurality of electrode layers, generally tabular in form is formed in a stack, the outermost layers providing electrical contacts, and defining a first electrical current path through the stack. Two sidewall conductor layers are formed to abut either end of the electrode layer stack, two sidewall conductor layers defining a second electrical current path. The ends of the sidewall conduction layers lie in the same planes as the electrode layer electrical contacts, such that electrode structure electrical contacts are each formed from one set of sidewall layer ends and an electrode layer electrical contact.

Abstract: A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.

Abstract: An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations.

Abstract: Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.

Abstract: A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-? material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.

Abstract: A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.

Abstract: A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.

Abstract: In an ultrasound imaging system that applies a beamformer to received ultrasound signal samples to form one or more beams represented by arrays of beamformed samples, a method and an apparatus compress each array of beamformed samples independently of the other arrays to form compressed beams. A plurality of analog to digital converters sample multiple analog ultrasound signals produced by a transducer array to provide multiple streams of ultrasound signal samples to the beamformer. The compressed beams are transferred via a digital interface to a signal processor. At the signal processor, the compressed beams are decompressed to form decompressed beams. The signal processor further processes the decompressed beams for diagnostic imaging, such as for B-mode and Doppler imaging, and scan conversion to prepare the resulting ultrasound image for display. This abstract does not limit the scope of the invention as described in the claims.

Abstract: Roughly described, a tiered storage system has a filesystem that promotes and demotes data among tiers at block granularity. It maintains a logical-to-physical mapping which indicates for each block in a file both the assigned tier and the physical block number within the tier. Methods for performing file- and block-level manipulations are described. In an embodiment, a nominal tier is managed by a native filesystem, and higher tiers are managed by a super filesystem. The super filesystem manages promotion and demotion among the tiers, interfacing with higher tiers directly but interfacing with the nominal tier only through the native filesystem. The native filesystem defines the file namespace in the system, and the logical-to-physical block mapping for blocks in the nominal tier. The super filesystem defines the logical-to-physical mapping for blocks in the higher tiers, but retains the file identification information as defined by the native filesystem.

Abstract: A device includes a substrate having a first region and a second region. The first region comprises a first field effect transistor having a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal.

Abstract: An integrated circuit includes a plurality of memory cells on a substrate, in which a first set of memory cells uses a first memory material, and a second set of memory cells uses a second memory material. The first and second memory materials have different properties such that the first and second sets of memory cells have different operational memory characteristics, such as switching speeds, retention and endurance.

Abstract: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.

Abstract: A security analyzer analyzes a security of a device-under-analysis (DUA). In one embodiment, the security analyzer identifies two or more valid message-delivery preconditions for a communication protocol supported by the DUA. One of the identified valid message-delivery preconditions is selected and the security analyzer delivers an attack to the DUA according to the selected message-delivery precondition. The same or similar attacks can also be delivered to the DUA via other message-delivery preconditions. Based on the DUA's response, the security analyzer determines whether a vulnerability has been found.