Abstract: A memory device with a thin heater forms a programmable resistive change region in a sub-lithographic pillar of programmable resistive change material (“memory material”), where the heater is formed within the pillar between the top electrode and the programmable material. The device includes a dielectric material layer and vertically separated top and bottom electrodes having mutually opposed contact surfaces. A sub-lithographic pillar of memory material, which in a particular embodiment is a chalcogenide, is encased within the dielectric material layer. A heater between the pillar of programmable resistive material and the top electrode forms an active region, or programmable resistive change region, next to the heater when the memory device is programmed or reset.

Abstract: A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change element positioned between and electrically coupling the opposed contact elements of the electrodes to one another. The phase change element has a width, a length and a thickness. The length, the thickness and the width are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the length and the width of the phase change element are each less than the minimum photolithographic feature size.

Abstract: A delivery system for an implantable vascular prosthesis is provided for a vascular prosthesis including at least first and second helical sections having alternating directions of rotation that are coupled to one another at apices. The delivery system includes an elongate body, a plurality of retainers and an outer sheath. The plurality of retainers are configured to temporarily retain a plurality of inner wound apices of the vascular prosthesis. The outer sheath is configured to retain the vascular prosthesis in a contracted state on the elongate body.

Abstract: Machine readable documents connect businesses with customers, suppliers and trading partners. The self defining electronic documents, such as XML based documents, can be easily understood amongst the partners. Definitions of these electronics business documents, called business interface definitions, are posted on the Internet, or otherwise communicated to members of the network. The business interface definitions tell potential trading partners the services the company offers and the documents to use when communicating with such services. Thus, a typical business interface definition allows a customer to place an order by submitting a purchase order or a supplier checks availability by downloading an inventory status report. Also, composition of the input and output documents, coupled with interpretation information in a common business library, programs the transaction in a way which closely parallels the way in which paper based businesses operate.

Abstract: A method is described herein for predicting lateral position information about a feature represented in an integrated circuit layout for use with an integrated circuit fabrication process, where the process projects an image onto a resist. The method includes providing a lateral distribution of intensity values of the image at different depths with the resist. Next, the lateral position of an edge point of the feature is predicted in dependence upon a particular resist development time, and further in dependence upon the image intensity values at more than one depth within the resist.

Abstract: A signal compression method and apparatus for a base transceiver system (BTS) in a wireless communication network provides efficient transfer of compressed signal samples over serial data links in the system. For the uplink, an RF unit of the BTS compresses baseband signal samples resulting from analog to digital conversion of a received analog signal followed by digital downconversion. The compressed signal samples are transferred over the serial data link to the baseband processor then decompressed prior to normal signal processing. For the downlink, the baseband processor compresses baseband signal samples and transfers the compressed signal samples to the RF unit. The RF unit decompresses the compressed samples prior to digital upconversion and digital to analog conversion to form an analog signal for transmission over an antenna. Compression and decompression can be incorporated into operations of conventional base stations and distributed antenna systems, including OBSAI or CPRI compliant systems.

Abstract: Random partial shared secret recognition is combined with using more than one communication channel between server-side resources and two logical or physical client-side data processing machines. After a first security tier, a first communication channel is opened to a first data processing machine on the client side. The session proceeds by delivering an authentication challenge, identifying a random subset of an authentication credential, to a second data processing machine on the client side using a second communication channel. Next, the user enters an authentication response in the first data processing machine, based on a random subset of the authentication credential. The authentication response is returned to the server side on the first communication channel for matching. The authentication credential can be a one-session-only credential delivered to the user for one session, or a static credential used many times.

Abstract: Embolic protection and plaque removal apparatus and methods are provided wherein an aspiration device aspirates, filters and reperfuses blood using a closed fluid circuit having a bi-directional working lumen. The plaque removal device includes a plurality of self-expanding cutting elements that form a cage that self-centers within the blood vessel to reduce the risk of trauma to the vessel lining.

Abstract: A method for transmitting data by means of a data processing system, the system being capable of supporting an operating system and at least one application and having access to a memory and a network interface device capable of supporting a communication link over a network with another network interface device, the method comprising the steps of: forming by means of the application data to be transmitted; requesting by means of the application a non-operating-system functionality of the data processing system to send the data to be transmitted; responsive to that request: writing the data to be transmitted to an area of the memory; and initiating by means of direct communication between the non-operating-system functionality and the network interface device a transmission operation of at least some of the data over the network; and subsequently accessing the memory by means of the operating system and performing at least part of a transmission operation of at least some of the data over the network by means

Abstract: An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model.

Abstract: A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices.

Abstract: A memory cell comprising: a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region; a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed above the channel region; a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region; a charge trapping structure disposed above the conductive layer and above the channel region; a top dielectric structure disposed above the charge trapping structure and above the channel region; and a top conductive layer disposed above the top dielectric structure and above the channel region are described along with devices thereof and methods for manufacturing.

Abstract: A manufacturing method for stacked, non-volatile memory devices provides a plurality of bitline layers and wordline layers with charge trapping structures. The bitline layers have a plurality of bitlines formed on an insulating layer, such as silicon on insulator technologies. The wordline layers are patterned with respective pluralities of wordlines and charge trapping structures orthogonal to the bitlines.

Abstract: A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist, which can be analyzed by standard verification tools and by other tools that operate on netlists. The correctness of such systems can require reasoning about a much smaller number of memory entries than exist in the circuit design, and by abstracting such memories to a smaller number of entries, the computational complexity of the verification problem is substantially reduced.

Abstract: An electronic filter operates as a correlator that provides a discrete approximation of an analog signal. The analog to digital conversion is integrated directly approximation calculation. An array of sample and hold circuits or single bit comparators provide outputs to a series of multipliers, the other input of which is a coefficient value of a Fourier series approximation of the desired frequency response. Each of the sample and hold circuits samples sequentially in time and holds its sample until the next cycle. Thus the sample point rotates in time through the array and each new sample is multiplied by a different coefficient. The output of the multipliers is summed for evaluation.

Abstract: A memory device includes two electrodes, vertically separated and having mutually opposed contact surfaces, between which lies a phase change cell. The phase change cell includes an upper phase change member, having a contact surface in electrical contact with the first electrode; a lower phase change member, having a contact surface in electrical contact with the second electrode; and a kernel member disposed between and in electrical contact with the upper and lower phase change members. The phase change cell is formed of material having at least two solid phases, and the lateral extent of the upper and lower phase change members is substantially greater than that of the kernel member. An intermediate insulating layer is disposed between the upper and lower phase change members adjacent to the kernel member.

Abstract: A system for identifying characteristics of communication circuit devices in a communication circuit includes a stimulus signal generator configured to generate a stimulus signal at a plurality of amplitudes for the communication circuit devices. At least one of the plurality of amplitudes exceeds a first predetermined threshold. At least one communication circuit device is configured to generate a signature signal in response to the stimulus signal when the stimulus signal exceeds the first predetermined threshold. The system includes an evaluation device configured to evaluate at least one intermodulation distortion (IMD) product of the signature signal generated by the at least one communication circuit device, and to identify a class of the at least one communication circuit device according to a transition level of an amplitude of the at least one IMD product of the signature signal that exceeds a second predetermined threshold.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Adjacent memory devices are electrically isolated. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A method, a computer medium storing computer instructions performing a method, and a computer with processor and memory perform stress modeling as follows. The stress model transforms a representation of a material conversion of a first material in the integrated circuit to a second material in the integrated circuit. Prior to the material conversion the first material occupies a first space having a first boundary. After the material conversion the first material and the second material together occupy a second space having a second boundary. The first space and the second space are different. The stress model performed by the computer system transforms the representation of the material conversion of the first material to the second material into: i) the first material occupying the first space having the first boundary, and ii) a strain displacement condition of the first material. The strain displacement condition is determined by a spatial change from the first boundary to the second boundary.

Abstract: Methods of operating non-volatile memory devices are described. The memory devices comprise memory cells having an n-type semiconductor substrate and p-type source and drain regions disposed below a surface of the substrate and separated by a channel region. A tunneling dielectric layer is disposed above the channel region. A charge storage layer is disposed above the tunneling dielectric layer. An upper insulating layer is disposed above the charge storage layer, and a gate is disposed above the upper insulating multi-layer structure. A positive bias is applied to a word line of the memory device in a selected memory cell and a negative bias is applied to a bit line in the selected cell. In another memory device, opposite polarity voltages are applied to the bit line and the word line.