Abstract: The present invention relates to a tethered digital butler consumer electronics product and method. The tethered digital butler, of a price and form factor suitable for consumer electronics markets of developed and developing countries, includes a communications and multi-media console and a wireless remote. The remote may resemble a handheld personal computer (HPC), a palm-held personal computer (PPC or PDA) or a smart phone, but has a low cost and feature set supported by the console that is novel in the consumer electronics market. In particular, this disclosure relates to combining telephone service, device control and, optionally, a fingerprint reader for easy user identification/authorization and personalization. As another option, a camera can be incorporated into the remote, thereby enabling video conferencing and other visual features.

Abstract: The present invention is directed to an implantable vascular prosthesis configured for use in a wide range of applications, such as treating aneurysms, maintaining patency in a vessel, and providing controlled delivery of therapeutic agents to a vessel wall. The prosthesis comprises a helical body having a plurality of turns, wherein the proximal and distal edges of the turns of the prosthesis has a pattern that interdigitates when the prosthesis assumes the deployed configuration. The prosthesis optionally may comprise a radially expanding distal portion coupled to the helical body for facilitating placement of the prosthesis within a body vessel.

Abstract: An Integrated circuit includes a plurality of memory cells on a substrate, in which a first set of memory cells uses a first memory material, and a second set of memory cells uses a second memory material. The first and second memory materials have different properties such that the first and second sets of memory cells have different operational memory characteristics, such as switching speeds, retention and endurance.

Abstract: A method, system and computer program product for programming a plurality of programmable resistive memory cells is disclosed. The method comprises executing the following for each memory cell: reading a resistance of a memory cell and reading input data corresponding to the memory cell. The method further comprises executing the following for each memory cell: programming the memory cell to a lower resistance (SET) state if the resistance is at a higher resistance state and the input data corresponds to a first (SET) state and programming the memory cell to a higher resistance (RESET) state if the resistance is at a lower resistance state and the input data corresponds to a second (RESET) state.

Abstract: A phase change memory cell includes first and second electrodes having generally coplanar surfaces spaced apart by a gap and a phase change bridge electrically coupling the first and second electrodes. The phase change bridge may extend over the generally coplanar surfaces and across the gap. The phase change bridge has a higher transition temperature bridge portion and a lower transition temperature portion. The lower transition temperature portion comprises a phase change region which can be transitioned from generally crystalline to generally amorphous states at a lower temperature than the higher transition temperature portion. A method for making a phase change memory cell is also disclosed.

Abstract: A multiphase clock generates pulses at a rate much higher than the clock frequency.

Abstract: Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.

Abstract: A network mobility server, which includes a target device inventory module, a data collection module, a data management module and a distribution module. The data management module, includes at least one data storage module, in which at least a portion of the data stored therein are identical data items stored in different selected formats suitable for use on mobile computing and telecommunication devices. The network also includes network agents, resident on numbers of the network members.

Abstract: A memory device includes bottom and top electrode structures and a memory cell therebetween. The memory cell comprises bottom and top memory elements and a dielectric element therebetween. A lower resistance conduction path is formed through the dielectric element. The dielectric element may have an outer edge and a central portion, the outer edge being thicker than the central portion. To make a memory device, an electrical pulse is applied through the memory cell to form a conduction path through the dielectric element. A passivation element may be formed by oxidizing the outer surface of the memory cell which may also enlarge the outer edge of the dielectric element.

Abstract: A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.

Abstract: Compression of signal samples output from a parallel, time-interleaved analog to digital converter (TIADC) for a baseband signal, includes calculating first or higher order differences of consecutive signal samples followed by lossless or lossy encoding of the difference samples to produce compressed samples. Compression of a TIADC output signal with a nonzero center frequency, includes calculating sums or differences of pairs of signal samples separated by an appropriate number of sampling intervals followed by lossless or lossy encoding. The sums or differences of the signal samples have lower magnitudes than the original samples, allowing more efficient compression. Lossy compression alternatives produce compressed data with a fixed bit rate or with a fixed quality in the decompressed samples.

Abstract: An aspect of the present invention includes a protocol for conveying data during an e-commerce session with a polymorphic response, comprising initiating a session with a message from a buyer application to a broker application and a session identifier assigned by the broker application; conducting the session between the buyer application and a supplier application; and concluding the session with a additional message which includes a schema identifier for the additional message, resolvable in a context of a system identifier; and a polymorphic response comprising a type and a version, wherein the polymorphic response includes additional data elements corresponding to values assigned to the type and version.

Abstract: A memory device as described herein includes a memory member contacting first and second interface structures. The first interface structure electrically and thermally couples the memory member to access circuitry and has a first thermal impedance therebetween. The second interface structure electrically and thermally couples the memory member to a bit line structure and has a second thermal impedance therebetween. The first and second thermal impedances are essentially equal such that applying a reset pulse results in a phase transition of an active region of the memory member spaced away from both the first and second interface structures.

Abstract: A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the memory array. The high resistance state for the reference array is a “partial reset” state having a minimum resistance less than that of the high resistance state for the memory array. Sense circuitry is adapted to read the memory cells of the reference array and to generate a refresh command signal if there is a difference between a current data set stored in the reference array and an expected data set, and control circuitry responsive to the refresh command signal to perform a refresh operation on the memory cells of the memory array.

Abstract: A modular shade system with solar tracking panels includes a series of generally North-South oriented, spaced apart torque tubes, each torque tube having an axis, a series of panels mounted to at least some of the torque tubes to create spaced-apart rows of panels along the torque tubes, at least some of the panels being solar collector panels. The system also includes a shade structure, positioned at a selected location between selected ones of the torque tubes and above the support surface so to provide an enhanced shaded region thereunder, and a support structure. The support structure includes a first mounting assembly mounting each torque tube above the support surface for rotation about the axis of each torque tube and a second mounting assembly supporting the shade structure at the selected location. The system further comprises a tilting assembly selectively rotating each torque tube about its axis.

Abstract: A method of configuration controlling a hierarchy of data arrays is disclosed, each data array in the hierarchy having at least one version, each version of each data array in the hierarchy being associated with one version of at least one other data array in the hierarchy, each data array comprising at least one data entry, each data entry comprising a plurality of fields, the plurality of fields comprising a version field and at least one characteristic field having a characteristic, the version field indicating which version of that data array the associated characteristic fields belong to. The method comprises the steps of: (i) defining a package of data arrays comprising a predetermined version of at least two data arrays in the hierarchy and in which at least one of the data arrays is to be updated to a new version based on a previous version; and (ii) appending a new version indicator indicative of the new version to each data entry having the previous version in the at least one of the data arrays.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.

Abstract: A tracking solar collector assembly includes solar collector support structure, with at least one solar collector mounted thereto and first and second spaced apart pivotal support points defining a tilt axis, Southside supports, with first pivot connectors, and North side supports, with a base, a second pivot connector, and one or two support elements connected to the base and to the second pivot connector at the ends thereof. The first and second support points are pivotally connected to and supported by the first pivot connectors and by the North side supports, respectively. The assembly also includes a tilting assembly causing the solar collectors therewith to tilt in unison.

Abstract: Memory devices are described along with manufacturing methods. An embodiment of a memory device as described herein includes a conductive bit line and a plurality of first electrodes. The memory device includes a plurality of insulating members, the insulating members having a thickness between a corresponding first electrode and a portion of the bit line acting as a second electrode. The memory device further includes an array of bridges of memory material having at least two solid phases, the bridges contacting respective first electrodes and extending across the corresponding insulating member to the bit line. The bridges define an inter-electrode path between the corresponding first electrode and the bit line defined by the thickness of the insulating member.