Abstract: A DRAM circuit is disclosed with circuitry for disabling data output drivers to prevent bus contention during system power-up. The circuitry includes a counter for counting RAS (or CAS) signals, and for disabling the output data drivers until 7 RAS (or CAS) signals are counted. The output of the counter (called Keep Off) connects to each of the tri-state buffer output drivers, through an AND gate. Other inputs to the AND gate may include an output signal Pwrup from a voltage detection circuit, and other enable signals. The counter uses the RAS signals as a clock signal to three D flip-flops. The Pwrup signal also is used as a reset to each of the flip-flops. The Q output of the flip-flops are anded together, to produce a signal which is released when the count reaches 111.

Abstract: In a computer system having a plurality of devices coupled to a bus, the plurality of devices having a bus master mode allowing a selected one of the devices to function as a bus master and adapted to request designation as a bus master, an arbitration circuit and method of arbitration for determining which one of the plurality of devices is to function as the bus master when two of the plurality of devices coincidentally request the designation.

Abstract: A test apparatus and method for testing a port of a computer system. The port has a plurality of output lines and a single input line. The apparatus includes: (1) a receiver circuit for receiving a datum transmitted in parallel from the computer system via the plurality of output lines, (2) a storage circuit, coupled to the receiver circuit, for temporarily storing the datum from the output lines and (3) a transmitter circuit, coupled to the storage circuit, for serially transmitting the datum via the input line to the computer system. The computer system compares the datum transmitted from the computer system to the datum received by the computer system to verify a proper functioning of the output lines and input line.

Abstract: A docking station structure is used to operatively connect a notebook computer to desktop computer peripheral devices. In response to manual insertion of the computer into the interior of the docking station a motorized travel structure drives the computer further into the docking station and forcibly interconnects pin type connectors carried by the computer and the docking station. The docking station connector is supported for translational movement by a specially designed floating connector interface structure which permits the docking station connector to translationally shift, in response to forcible engagement by the computer connector portion when there is a misalignment between the computer and docking station connectors, in order to precisely align the two connectors before they are telescopingly mated with one another.

Abstract: A drive array controller is provided that serves as an interface between both stand-alone SCSI devices as well as SCSI devices that form a composite drive. Since an AHA emulation interface is incorporated on the drive array controller, the drive array controller is compatible with conventional AHA device drivers that drive stand-alone peripheral devices such as SCSI CD-ROM units and SCSI tape drives. The drive array controller includes a SCSI pass-through driver that extracts a SCSI command descriptor block from a command control block created by the AHA device driver. The drive array controller further provides a separate peripheral access channel to support high speed composite drive operations through a composite device driver. Since the AHA emulation interface and a composite drive interface are provided on a common peripheral board, only one EISA expansion slot is occupied.

Abstract: A cooling subsystem and method for a chassis of a computer system. The cooling subsystem comprises: (1) first and second cooling fans having first and second motors associated therewith for driving the first and second cooling fans, respectively and (2) a common plenum substantially shrouding and providing a pathway for air communication between the first and second cooling fans, the first and second fans cooperating to provide an optimum rate of air flow from without the chassis to within the chassis to provide air exchange within the chassis, the air flow within the chassis being in a predetermined direction to provide directed cooling of a specified device within the chassis, the common plenum allowing the first and second fans to continue to cooperate to provide a minimum air flow to provide a minimum air exchange within the chassis, the air flow remaining in the predetermined direction to continue the directed cooling of the specified device when a selected one of the first and second motors fails.

Abstract: The present invention provides, in a computer chassis containing a substantially planar removable expansion card therein, the computer chassis having an opening therein allowing access to the expansion card, a plane of the expansion card substantially parallel with a plane of the opening, a support structure for the expansion card and a method of supporting the expansion card.

Abstract: A method and apparatus which synchronizes signals operating at different clock speeds with reduced synchronization latency. The present invention is preferably used in systems where a first logic portion operating at a first clock speed, referred to as a fast clock speed, interfaces to a second logic portion operating at a second, slower clock speed. A new slow clock is generated pseudo-synchronously from the fast clock using a phase locked loop (PLL) clock generator. The PLL multiplies the fast clock frequency up to the least common multiple (LCM) of the two frequencies to generate a base clock signal. The base clock is then divided down to form the slow clock signal. The PLL performs its operations in such a way that all three clocks have a fixed phase relationship. The rising edges of the base clock, fast clock, and slow clock line up at periodic points and are skewed at other periodic points.

Abstract: A system for detecting and locating errors in printed wire assemblies contained in a device with capabilities of performing a power on self test (POST) comprised of testing subroutines. The system monitors the device during execution of the POST. If a run error occurs during the POST, the system, through its monitoring, receives an indication of the run error. The system then delivers to the device a command, external to the POST routine, which directs the POST routine to thereafter separately execute each of the testing subroutines of the POST. If a run error occurs in any testing subroutine as it is being separately executed, a signal indicative of the run error and particular testing subroutine in which it occurred is sent to the system.

Abstract: To reliably maintain an EMI grounding connection between a sheet metal computer chassis wall and a computer cover wall that may be removably placed against the outer side of the chassis wall, a lance structure is formed in the chassis wall, and opposing installation notches are formed in the chassis wall on opposite sides of the lance opening. Transversely enlarged end portions of an elongated arcuate sheet metal grounding strip are inserted inwardly through the wall notches and captively retained within the lance structure with a longitudinally intermediate portion of the arcuate strip body extending outwardly through the chassis wall lance opening. When the cover wall is operatively installed on the chassis wall the grounding strip is resiliently flattened and compressed between the lance strip and the installed cover wall to maintain an EMI grounding path between the contiguous chassis and cover walls.

Abstract: A feedback system coupled between both outputs of a dual flyback converter for detecting which output is loaded and for switching between one of two feedback circuits for regulating the voltage of the loaded output. The detection circuit includes a balanced voltage divider coupled in series between the two opposite polarity outputs. The voltage divider preferably comprises balanced high impedance resistors to prevent substantial loading. The voltage of the junction between the two resistors shifts away from the loaded output because of an increase of the voltage level of the unloaded output caused by leakage inductance of the switching transformer. The detection circuit also includes a comparator, which detects the voltage shift and asserts its output to a switch circuit, which switches control between the two feedback circuits to control the loop and appropriately regulate the loaded output voltage. The switch circuit is preferably an analog switch including one or more field-effect transistors.

Abstract: A dual processor computer system is disclosed that includes a processor failure detection and recovery circuit which initially designates one of the processing units as the lead-off master and the other processing unit as a slave. The processor failure detection and recovery circuit includes a timer unit which begins the countdown of a predetermined period in response to the initial resetting of the master and slave processors. The processor failure and detection circuit further includes a control unit which determines whether the master processor fails to reset or suffers from a hard failure by determining whether a bit of a storage unit has been set in response to software code intended for execution by the master processor during initialization. If the bit is not set before the lapse of the predetermined time period following reset, the control unit changes the designation of the slave processor to master and simultaneously resets the re-designated master.

Abstract: Disclosed are an apparatus and method for coupling a heat sink to a heat-producing electronic component, such as a microprocessor, into an assembly.

Abstract: A computer cover structure is removably slid over an associated computer chassis to place facing end walls of the cover and chassis in a contiguous, parallel relationship, the end walls are automatically aligned with one another, in two perpendicular directions parallel to their facing side surfaces, by a plurality of outwardly projecting lance strips associated with the cover structure end wall and received by corresponding elongated, generally diamond-shaped openings formed in the chassis end wall. The wall openings are longer and wider than the outwardly projecting longitudinally intermediate portions of the lance strips, and have oppositely sloped facing side edges. Initially, the longitudinally intermediate lance strip portions freely enter their associated chassis wall openings.

Abstract: A docking detection and suspend circuit for portable computer/expansion chassis docking system. A first circuit within the portable computer is capable of detecting an impending electrical coupling of the portable computer to a corresponding docking station and generating a signal indicating the impending coupling. A second circuit within the portable computer and coupled to the first circuit is capable of receiving the signal and placing the portable computer in a suspend mode at least until the portable computer fully electrically couples to the docking station. The present invention relieves a computer user of the task of manually placing the portable computer in the suspend mode prior to docking with the docking station. The present invention protects components within both the portable computer and the docking station from being damaged by docking the portable computer when in a normal operational mode and prevents the user's data from being corrupted.

Abstract: A system for controlling the rate and duration of battery charging. A microprocessor is connected in a battery current signal feedback loop and used to control the battery charge cycle. The rate of charge is gradually stepped up at the beginning of the charge cycle until the charging current reaches a defined maximum value, and thereafter maintained between the maximum and a defined minimum value for the duration of the charge cycle. The microcontroller terminates the charge cycle when the battery charging current begins to increase while the rate of charge remains constant, this being an indication that the battery is fully charged. Sensors input signals to the microcontroller to prevent or terminate charging if the battery cells are not within an appropriate temperature range, or if a short circuit or other adverse condition arises.

Abstract: A method and apparatus for performing cache snoop testing on personal computers using software to initiate DMA cycles. The computer system includes an extended capabilities parallel port (ECP), which includes a 16 bit first-in first-out buffer (FIFO) that can be accessed in a test mode where software can manually write and read the FIFO. This FIFO in the ECP parallel port is used according to the present invention to implement cache snoop testing diagnostics on personal computers. In the preferred embodiment, various hardware subsystems such as system memory, the ECP port, and the DMA controller are tested first to ensure that, if a failure occurs during cache testing, the system can differentiate between cache snoop failures and other subsystem failures. Cache snoop testing according to the present invention uses the capability provided by the ECP parallel port to generate DMA cycles which transfer data from the ECP FIFO buffer into the system memory via software.

Abstract: A specially designed metal grounding cap is placed over a metal-plated housing boss upon which a printed circuit board is to be mounted by extending a screw through a hole in the circuit board and tightening the screw into a metal insert previously forced into the free end of the mounting boss. As the screw is tightened into the boss insert, an EMI grounding pad on the underside of the circuit board engages an end wall of the grounding cap and pushes it into forcible engagement with the inner end of the boss. The forcible engagement of the grounding cap end wall causes leg portions of the cap to pivot inwardly and engage portions of the plated boss side wall between the boss insert and the metal plated housing wall from which the boss inwardly projects.

Abstract: Disclosed are a personal digital assistant ("PDA") and a method of providing data to the PDA. The PDA includes: (1) a chassis having first and second noncoplanar surfaces thereon and containing computer processing circuitry therein, (2) a visual display located on one of the first and second surfaces, the visual display coupled to the circuitry to allow the circuitry to drive the visual display and (3) a plurality of momentary keys located on both of the first and second surfaces and coupled to the circuitry, the plurality cooperating to form a chord keyboard to thereby allow multiple ones of the plurality to be depressed at a time to form a chord, the circuitry interpreting the chord as a single keystroke.

Abstract: A firing head adapted to connected between a coiled tubing and a perforating gun, is sized and shaped to enable it to move freely within a tubing string in the wellbore, may be actuated by fluid pressure within the coiled tubing, and includes a circulation and recirculation feature wherein wellbore fluid may be circulated through the firing head between the coiled tubing and an annulus around the tubing string, the circulation taking place either before or after detonation of the perforating gun. Three firing heads are discussed. One such firing head is a Circulation Direction Firing (CDF) Head. The CDF firing head circulates fluid from the wellbore to the coiled tubing and depresses a piston. Then, fluid pressure from the coiled tubing lifts the piston uncovering locking balls and propelling a firing pin to a booster of a detonating cord detonating the CDF firing head. Fluid circulation from the coiled tubing to the wellbore annulus begins after the CDF firing head detonates.