Abstract: Compounds of Formula I ##STR1## are disclosed as inhibitors having activity against the aspartyl proteases, plasmepsin and cathepsin D. The compounds are therefore useful for treatment of diseases such as malaria and Alzheimer's disease. In preferred compounds of Formula I, Y is an dialkoxyphosphonate, or .alpha.-hydroxyamide group and Z is an acyl or .alpha.-ketocarbamate functionality. Intermediates in the solid phase synthesis of compounds of Formula I, in which compounds are attached to a solid support, are also disclosed.

Abstract: A regulator is provided for establishing asymmetrical voltage increase/decrease capability between an input node and an output node for enhanced regulation of either a voltage sag or a voltage swell within a utility system. The regulator includes an autotransformer having an input tap coupled to the input node of the regulator and an output tap coupled to the output node. The regulator further includes an electronic tap changer system coupled to the winding of the autotransformer. Together, the autotransformer and the electronic tap changer system provide the regulator with its asymmetrical voltage increase/decrease capability between the input node and the output node thereof. The regulator can be configured for voltage increase only, voltage decrease only, or both, provided an asymmetrical voltage increase/decrease capability is defined.

Abstract: A chemical mechanical planarization tool and method are presented employing a non-linear motion of the carrier arm relative to the polishing pad. The non-linear motion of the carrier arm relative to the polishing pad can be accomplished in a variety of ways, for example, employing a mechanical template having an irregular opening or programming the carrier displacement mechanism to move the carrier in an irregular, non-rotational X-Y path over the polishing pad.

Abstract: A programmable self-time refresh circuit for a semiconductor memory and methods for programming the self-refresh rate for non-invasively and deterministically testing the self-timed refresh circuit for establishing/verifying a refresh rate and a wait state interval for the self-refresh operation. The programmable refresh circuit includes a self-timed oscillator that outputs a clocking signal, and a programmable pattern generator that outputs a first signal pattern and a second signal pattern. The first signal pattern is fed to a counter circuit which also receives the clocking signal. The counter circuit outputs a signal pulse whenever the count driven by the clocking signal reaches a digital pattern representation corresponding to the first signal pattern generated by the programmable pattern generator. Refresh control logic is connected to receive the pulse signal and respond thereto by refreshing a portion of the memory array of the semiconductor memory device.

Abstract: A semiconductor device has an on-board decoupling capacitor provided at its interconnect region. The decoupling capacitor comprises two layers of metallurgy separated by a dielectric layer wherein two of the layers are identically patterned.

Abstract: Lawn and garden maintenance equipment for collecting and shredding debris and chipping branches is provided with wheel support, a housing, and a handle for guiding the apparatus, the housing having a substantially closed bottom wall below a motor-driven disc for rotation about a vertical axis, which disc is capable of chipping branches because of a knife on one side and of moving air because of blades on the other side. A circumfirentially extending screen within the housing is supported in a vertical orientation relative to the ground, which screen is formed of at least two segments, both of which are supported radially inwardly and spaced from the sidewalls of the housing. The air and entrained debris are drawn into and enters the housing through an inlet extending to a centrally disposed axial opening whereby the entrained air and debris are driven against the screen to be broken up into smaller pieces.

Abstract: A chimney capacitor is formed having two plates, of which each is disposed above and contacts a corresponding electrical contact. The electrical contacts facilitate electrical access to the plates of the chimney capacitor. One of the electrical contacts may comprise part of a general wiring layer that may be used for both electrically accessing the capacitor and for general wiring within the IC chip. Formation of the chimney capacitor proceeds by first forming two electrical contacts on an integrated circuit ("IC") chip. A planar insulating layer is formed thereover, and the capacitor is formed at least partially within the planar insulating layer such that each plate is electrically connected to a corresponding electrical contact.

Abstract: Improved, planarized semiconductor structures are described which are prepared by a method involving the creation of a series of subminimum (i.e., 50 to 500 angstroms thick) polysilicon pillars extending vertically upward from the base of a wide trench and depositing a conductor material by chemical vapor deposition over the pillars; the pillars prevent the formation of a depression within the trench when planarized.

Abstract: A structure and method for removing and recovering an anodically bonded glass device from a substrate using a metal interlayer interposed between the glass and the substrate is provided. As used in semiconductor mask fabrication, the structure comprises a silicon wafer substrate coated with a membrane on which a metal interlayer is disposed. The metal interlayer and a glass device are anodically bonded together. Recovery of the glass device is accomplished by chemically and mechanically removing the wafer and its membrane from the metal interlayer. The membrane is preferably removed using reactive ion etching to which the metal interlayer is resistant. The metal interlayer is then removed from the glass device using a highly corrosive chemical solution. The recovered glass device may then be reused.

Abstract: An improved semiconductor structure is disclosed, including at least one stud-up and an interconnection line connected thereto, wherein the stud-up and interconnection line are formed from a single layer of metal. The structure is prepared by a method in which an insulator region is first provided on a semiconductor substrate, and is then patterned and etched to define at least one opening having a pre-selected depth. Metal is deposited to fill the opening and form the interconnection line, followed by the patterning and formation of a stud-up of desired dimensions within the metal-filled opening. The lower end of the stud-up becomes connected to the interconnection line, and the upper end of the stud-up terminates at or near the upper surface of the insulator region. Other embodiments also include an interconnected stud-down.An endpoint detection technique can be used to precisely control the height of the stud-up and the width of the interconnection line.

Abstract: An induction device has an elongated core made of two or more uniform ferromagnetic spaced-apart toroids. A first winding around the core creates an inductor. When the induction device includes a second winding, a transformer is created. The transformer acts as a powercord transformer when the exposed ends of one winding are available at one end of the elongated core for connection to a source of alternating current and the exposed ends of the other winding are available at the other end of the core for connection to a load. An inductor with a single-turn winding can be constructed by first forming the core by stacking two or more ferromagnetic toroids end-to-end and spaced apart, then threading two wires through the core center and placing two wires outside the core and connecting the ends of the wires to create the winding. A transformer can be constructed by first following the steps to create an inductor. A second winding is then created in a similar manner as the first winding.

Abstract: A process is disclosed for making circuit elements by photolithography comprising depositing an antireflective polyimide or polyimide precursor layer on a substrate and heating the substrate at 200.degree. C. to 500.degree. to provide a functional integrated circuit element that includes an antireflective polyimide layer. The antireflective polyimide layer contains a sufficient concentration of at least one chromophore to give rise to an absorbance sufficient to attenuate actinic radiation at 405 or 436 nm. Preferred chromophores include those arising from perylenes, naphthalenes and anthraquinones. The chromophore may reside in a dye which is a component of the polyimide coating mixture or it may reside in a residue which is incorporated into the polyimide itself.

Abstract: A plasma enhanced chemical vapor deposition process for producing a fluorinated silicon nitride film on a substrate is disclosed. The process utilizes a mixture of silane, perfluorosilane and nitrogen to produce films of high conformality and stability. The silane and perfluorosilane in the mixture are in a ratio of 0.05 to 1 on a volume basis. The preferred silane is SiH.sub.4 and the preferred perfluorosilane is SiF.sub.4. Films prepared by the process are disclosed and their properties are described.

Abstract: An automated method for optimally ordering macros within a semiconductor chip data-path stack is disclosed. Each stack macro is assumed to have at least one predetermined bus connection with another macro in the stack. The ordering technique is based on minimizing for each macro in the stack the total number of stack macros passed by buses predeterminedly connected to that macro without making connection thereto. In addition, a macro group is formed of any subset of stack macros caught in a repeating loop. Each macro group contains at least two macros of the stack. Once defined, a macro group is treated as a single stack macro and optimization processing continues. Once the optimal location of all macros is identified, then any formed macro group is expanded and the optimal location of each macro within the group itself is identified. Specific details of the method are provided herein.

Abstract: Video subsystem power savings are achieved by shutting off power to unused subcircuits during blanking. Digital circuitry within the video subsystem not used during blanking is shut-down by turning off the clock thereto. Analog circuitry within a digital to analog converter is shut-down by turning off the constant current reference thereto. A functional unit containing digital circuitry within a serializer palette digital to analog converter (SPDAC) is shut-down by turning off the clock thereto during system operation in a mode where the functional unit is not utilized. A computer system having a monochrome display saves power by shutting off DAC digital circuitry clocks and DAC analog circuitry constant current references of all DACs but one. A portable computer with a liquid crystal display (LCD), a SPDAC for driving an external display and a LCD controller, saves power by shutting down video subsystem functional units and analog DAC circuitry not used for driving the LCD.

Abstract: A process is disclosed for making circuit elements by photolithography comprising depositing an antireflective polyimide or polyimide precursor layer on a substrate and heating the substrate at 200.degree. C. to 500.degree. to provide a functional integrated circuit element that includes an antireflective polyimide layer. The antireflective polyimide layer contains a sufficient concentration of at least one chromophore to give rise to an absorbance sufficient to attenuate actinic radiation at 405 or 436 nm. Preferred chromophores include those arising from perylenes, naphthalenes and anthraquinones. The chromophore may reside in a dye which is a component of the polyimide coating mixture or it may reside in a residue which is incorporated into the polyimide itself.

Abstract: The present invention provides an apparatus and method for monitoring the functioning of a special operational mode on an integrated circuit module without the need for a special or dedicated pin. By monitoring the data output pins of the module operation in a special operational mode and premature interruption thereof, is detected. Delayed transition from a state of low impedance to a state of high impedance during the data output cycle is indicative of the special operational mode. The modules which usually have tri-state devices on their output lines are provided with delay circuitry to delay the transition of the tri-state device, during the data output cycle, from a state of low impedance to a state of high impedance while the device remains in a special operating mode.

Abstract: The subject invention provides a method of enhancing the etch rate of boron nitride which comprises doping a layer of boron nitride with an element from Group IVA of the Periodic Table of the Elements, such as silicon, carbon, or germanium. The doped boron nitride layer can be wet etched at a faster rate with hot phosphoric acid than was possible prior to doping the boron nitride.

Abstract: A bearing setting procedure for a pair of bearings mounted on a spindle or an axle. Mounted on the spindle or axle are two bearings, each having an inner bearing race. Interposed between the inner bearing races is an adjustable spacer. A mechanism is employed for adjusting the bearings and collapsing the spacer such that a desired bearing tension is provided. In particular, the mechanism includes a piston extension which engages one of the inner bearing races when hydraulic pressure is applied to the piston extension. By applying the pressure, one of the inner bearing races moves closer to the other causing the adjustable spacer to collapse such that a desired bearing tension is provided.

Abstract: An interconnection array layout and method are provided for a plurality of paired line conductors of a given length extending principally parallel. A single crossing region traverses the paired line conductors intermediate the given length, wherein the line conductors of each pair of line conductors cross such that inter-pair capacitive coupling is matched. Intra-pair capacitive coupling is avoided by separating the line conductors of each pair of line conductors by two pitches and disposing therebetween a line conductor of a different pair of line conductors. Applications include semiconductor memory arrays, such as DRAM structures, and address/data busses wherein paired true/complement line conductors are employed.