Abstract: A computer system including a central processing unit (CPU) and a power management circuit (PMC). The CPU has an active mode where it is responsive to interrupt and direct memory access requests, and a standby mode where it is in a low power state and is not responsive to the interrupts and direct memory access requests. The PMC monitors the interrupts and direct memory access requests in the system when the CPU is in the standby mode, and causes the CPU to enter the active mode upon the detection of either an interrupt or a direct memory access request.

Abstract: A method of resetting the screen display mode in a computer system having a display monitor is disclosed. The method is arranged to reset the display mode while a designated operating system such as a windowing environment based operating system is running, without requiring the operating system or any currently running application(s) to be exited and reloaded. The method includes the step of receiving a user initiated input requesting a change in the display mode. After a display mode request is received, the operating system display characteristic variables are reset to values that are appropriate for the requested display mode. Additionally, the display driver display characteristic variables are reset to values that are appropriate for the requested display mode. Moreover, the hardware mode is set to a mode that is appropriate for the requested display mode.

Abstract: A sensing arrangement for sensing the addition of reactants to a solution within a tank which includes a first inlet, a second inlet, and a reactant supply controller for controlling the addition of reactants into the tank through the first and second inlets. The first inlet is configured to supply a first reactant to the tank and the second inlet is configured to supply a second reactant to the tank. The sensing arrangement comprises a detector, such as a conductivity detector or an ion concentration detector, having a probe for measuring the presence of the reactants in the solution within the tank. The probe is positioned substantially adjacent the second inlet. The detector provides a mechanism for measuring the presence of and concentration of the first reactant in the solution while the first reactant is added to and mixed with the solution.

Abstract: An integrated circuit assembly includes a dielectric flex tape substrate defining a predetermined array of electrically conductive traces and an array of solder balls or solder columns electrically connected to the bottom surface of the flex tape substrate and the traces. An integrated circuit die having a series of input/output pads is supported on the substrate. In one embodiment, a plurality of electrically conductive leads are supported by the flex tape substrate in electrical isolation from and over the conductive traces. A first and second series of bonding wires electrically connect certain ones of the input/output terminals on the integrated circuit die to the electrically conductive leads and conductive traces, respectively. In other embodiments, one or more electrically isolated conductive layers are supported by the dielectric flex tape substrate over the traces and electrically conductive leads.

Abstract: An apparatus for disabling a watchdog function of a watchdog circuit when a watchdog input pin of the watchdog circuit fails to receive an externally pulsed signal, which has a first predefined period. The watchdog circuit, while the watchdog function is enabled, generates a watchdog fault condition if the externally pulsed signal is not received at the watchdog input pin by the end of a predefined watchdog timeout period. The apparatus includes a pulse generation circuit for generating a pulsed signal having a second predefined period, the second predefined period being shorter than the watchdog timeout period. Further, the apparatus includes a drive circuit coupled to the pulse generation circuit and the watchdog input pin. The drive circuit provides an internally pulsed signal to the watchdog input pin at a predefined current level, responsive to the pulsed signal from the pulse generation circuit.

Abstract: A user interface is disclosed that facilitates easy find and display operations that search through the memory of a pointer based computing system. The user interface includes searching methods that are particularly well suited for use in a computer system in which the contents of the memory are divided into a plurality of searchable application files that are each capable of containing a plurality of records. In one aspect of the invention an improved find dialog box is disclosed. In another aspect, a method of selecting local verses global searches together with a method of conducting the chosen search and processing user inputs in response to the search results is disclosed. Additionally, an improved interface for displaying the results of various searches is described.

Abstract: A variety of methods of coordinating communications between a plurality of remote units and a central unit to facilitate communications using a frame based discrete multi-tone (DMT) transmission scheme am disclosed. In one aspect of the invention, synchronized quiet times are periodically provided in the upstream communication stream. The synchronized quiet times are used to handle a variety of control type functions such as synchronization of new remote units, transmission channel quality checking and handling data transfer requests. The information received is used to facilitate the dynamic allocation of bandwidth during use. In another aspect, a data request signal may be used to indicate either a desire to transmit at a particular data rate or a desire to transmit a particular amount of information. In the former case, the central unit allocates sufficient sub-channels to the remote unit to facilitate transmission at a requested data rate that is specified in the data request information.

Abstract: An integrated circuit package assembly incorporating an electrostatic discharge (ESD) interposer is disclosed. The assembly includes a semiconductor chip including a plurality of chip input/output terminals. The interposer is formed using a substrate which supports the chip and includes an arrangement having a plurality of integrally formed ESD protection circuits for providing ESD protection to predetermined ones of the chip input/output terminals.

Abstract: A method and apparatus for providing computer-assisted implicit and explicit assistance. If no implicit assist actions are desired or indicated, a logical process is initiated to determine whether explicit assistance should be undertaken. If implicit assistance is indicated, a list of action alternatives is displayed for the user. If explicit assistance is desired by the user, particular object(s) from which the assistance may be inferred are entered into an assistance operation. An attempt is made to recognize possible intents expressed by the objects entered into the assistance process. If no user intent is, in fact, recognized, the assist operation is usually terminated. If a possible intent is recognized, the actual intent is hypothesized. A check is further undertaken, to determine whether a hypothesis is in fact available. If no hypothesis is found, the process permits the user to supply a proposed action. If no hypothesis is found and no user action is proposed, assistance efforts terminate.

Abstract: A method of creating an editor that is executed on a first computer system is disclosed in which the editor is arranged to facilitate the editing of data from a first application program executed on a second computer system without requiting that the first application program run on the first computer system. The method includes the steps of creating a display info array that identifies the data fields that may be displayed in a data browser window portion of the editor and creating an edit info array that identifies the data fields may be edited in a detail window portion of the editor. In a preferred embodiment, validation scripts that define the types of data that may be accepted in each of the data fields that is set forth in the edit info array are identified, with the validations scripts forming a portion of the edit info array. This arrangement facilitates editing data using a foreign computer system.

Abstract: An integrated circuit structure including a conductive layer, a first dielectric layer overlying the conductive layer, a second dielectric layer overlying both the first dielectric layer and the conductive layer and a planarizing layer overlying the second dielectric layer. The conductive layer has a lateral dimension which is greater than a corresponding lateral dimension of the first dielectric layer. Thus the conductive layer and the first dielectric layer form a stepped, pyramidal shaped island. As a result of the stepped, pyramidal shape, the overlying planarizing layer forms with a more planar upper surface than if the sidewall of the island had a vertical profile. In one preferred embodiment of the present invention, the conductive layer is formed from tungsten-silicide, and both of the dielectric layers are either silicon dioxide or silicon nitride.

Abstract: A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.

Abstract: The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveabilility, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.

Abstract: The present invention discloses the use of a dielectric substrate panel suitable for supporting a plurality of independently packaged ICs. The substrate panel has a plurality of conductive landings arranged on its top surface, a plurality of conductive contacts arranged on its bottom surface and a multiplicity of electrically conductive vias. The vias pass through the substrate panel and are arranged to interconnect selected landings with their associated conductive contacts. The top surface of the substrate panel also includes a number of die attach areas. During packaging, dies are secured to their associated die attach areas on the substrate panel and electrically coupled to appropriate conductive landings. An encapsulant is then formed over each of the dies for protection.

Abstract: A method and apparatus for providing a translucent overlay image over a base image on the screen of a computer system. The method includes the steps of running an application program on a central processing unit (CPU) of a pen computer system to produce a base image in a screen coupled to the CPU; and running an overlay program on the CPU to produce an overlay image on the screen such that portions of the base image which are overlapped by the overlay image are at least partially visible through the overlay image. The overlay program is a computer implemented process comprising the steps of displaying an overlay image on the screen, intercepting screen inputs which contact the overlay image, processing the intercepted screen inputs in the CPU, and updating the application program based on the processed screen inputs.

Abstract: The present invention provides a tape printing device for printing a desirable series of characters on a tape and cutting the tape to a label of a desirable length, and also a tape cartridge used in the tape printing device. The tape cartridge has a characteristic element readably storing specific information on the tape such as a width of the tape. The tape printing device reads the characteristic element to control printing conditions according to the type of the tape cartridge. More specifically, the tape printing device determines a variety of parameters including a number of lines and character sizes of the character series printed on the tape as well as lengths of left and right margins. When a tape of a relatively large width is set in the tape cartridge, the device increases a rotation torque of a platen for feeding the tape.

Abstract: A method is provided for accurately determining the propagation delay of a gate under consideration in a static timing analyzer. This is accomplished by determining both the output load and input rise time of the gate under consideration. These values are then compared with a load versus rise time grid having previously determined values of propagation delay (points) for specified combinations of load and input rise time. These points are then used to interpolate a value of propagation delay for the gate under consideration by an interpolation technique that accounts for at least one of the following non-linear effects: the feed forward capacitance of a gate, soft switching, gate resistance, source and drain resistance, and/or other non-linear effects. The method accounts for each non-linear effect by imparting a corresponding component to propagation delay only in that range of output load and input rise time for which that non-linear effect is most pronounced.

Abstract: A solderable lead frame is disclosed which includes a copper base lead frame containing a one layer or plated tin or tin alloy and another layer of plated palladium. The tin plating covers only external portions of the leads, whereas the palladium covers the external regions including the tin plating, and extends into internal portions of the lead frame. A diffusion barrier, of cobalt or nickel, is provided on the base lead frame beneath the tin plating.

Abstract: Disclosed is a wafer clamp which holds a wafer in place during chemical vapor deposition processes. The wafer clamp includes (1) a clamp body having an inner facing portion and an outer facing portion; and (2) an overhang member attached to and extending inwardly from the inner facing portion of the clamp body. The clamp is designed such that when it holds the wafer, the overhang member extends over the wafer's peripheral region and is separated from that peripheral region by at least a predefined distance. The peripheral region is a region on the wafer's upper face that resides near the perimeter of the upper face. The predefined distance is chosen such that during deposition, a layer of material does not contact both the wafer face and the overhang member. The predefined distance is at least about 100 times the thickness of the layer of material.

Abstract: A method and apparatus for communication configuring in digital equipment based on the location of the equipment includes a mechanism determining the location of the digital equipment and a mechanism configuring a communication channel of the equipment based on the location. The location may be determined using a Global Positioning System, Global Paging System, or similar wireless communication system, or by connection to a wired network. User input may also be used in determining, in part or in whole, the location of the digital equipment. Once the location of the digital equipment has been determined, the communication channel for the digital equipment is configured based upon the location using configuration data stored with the digital equipment.