Abstract: A process and system and for extracting and refining gold from ores using relatively benign and inexpensive chemicals, fewer process steps, and permitting the recycling and re-use of process chemicals. The invention is preferably implemented as a two part process. In a first part process, gold is extracted from the ore and dissolved in a chemical solution to form a gold complex. The chemical solution preferably includes a KI and I.sub.2. Optionally, Isopropyl alcohol is mixed with the KI and I.sub.2 to serve as an accelerant. In a second part process, the complex is reduced to gold from the solution, preferably by one of two methods. The first method precipitates the gold complex by washing and decomposing of the gold complex to form pure gold. The second method electrolytically plates the gold from the gold complex solution onto a cathode to obtain pure gold.

Abstract: A method for forming self-aligned landing pads on a substrate containing a pre-formed first conducting layer and a pre-formed first insulator, wherein the substrate further includes a patterned second insulator to form contact openings exposing the substrate. A second conducting layer in formed on the substrate. A photoresist layer is formed on the second conducting layer and patterned to transfer the pattern onto the second conducting layer. The second conducting layer is patterned to expose the first insulator. Then, an etching back process is performed to selectively remove more of the second conducting layer in order to form the self-aligned landing pads.

Abstract: Disclosed is a method for improving the selectivity of dielectric layers to photoresist layers and base layers. The method is performed in a plasma processing chamber, and the photoresist layer is coated over the dielectric layer. The method includes introducing an etchant source gas into the plasma processing chamber, which consists essentially of a CxFy gas and an N.sub.2 gas. The method further includes striking a plasma in the plasma processing chamber from the etchant source gas. The method additionally includes etching at least a portion of the dielectric layer with the plasma through to a base layer that underlies the dielectric layer. The method is also well suited for anisotropically etching an oxide layer with very high selectivities to Si, Si.sub.3 N.sub.4, TiN, and metal silicides.

Abstract: A VGA control circuit includes a differential control voltage generator having an input coupled to an external control voltage and having a pair of control voltage outputs, a transfer function compression region TFCR compensator coupled to the differential control voltage generator, and a TFCR detector coupled to the TFCR compensator and developing a compensator activation signal in response to the detection of a TFCR state in the transfer curve. A method for controlling a VGA circuit exhibiting transfer function logarithmic compression includes detecting when a VGA circuit is entering a logarithmic compression state, and applying an exponential compensation signal to the VGA circuit to cancel the compression state. A VGA system includes a VGA control system developing a plurality of differential control signals and a plurality of VGA stages coupled to the plurality of differential control signals.

Abstract: A system and method are provided for separating water from a solvent during dry cleaning. Included is an inlet capable of receiving a mixture of dry cleaning fluid and water from a basket of a dry cleaning apparatus. The dry cleaning fluid includes a siloxane composition. Also provided is a flow controller for urging a flow of the mixture received from the outlet. Coupled to the flow controller is a coalescent media that receives the mixture urged by the flow controller. A chamber is coupled to the coalescent media for receiving the mixture from the coalescent media to separate the water and the dry cleaning fluid. Also coupled to the chamber is an outlet to remove the dry cleaning fluid from the chamber in the absence of the water.

Abstract: A method for fabricating an electrostatic discharge (ESD) protection circuit on a substrate is provided. The substrate includes an internal circuit region and an ESD protection region. A first MOS transistor is formed at the internal circuit region including a first gate structure, a first spacer, a first source/drain region with a first lightly doped drain (LDD) structure. A second MOS transistor is formed at the ESD protection circuit region including a second gate structure, a second spacer, a second source/drain region with a second LDD structure. The method includes forming a conformal metal layer over the substrate. A patterned photoresist layer is formed on the metal layer to expose a portion of the metal layer. Under the exposed portion of the metal layer it includes the second spacer and a portion of the second source/drain region.

Abstract: A method of optical proximity correction suitable for use in a mixed mode photomask. An original pattern is to be -transferred from the mixed mode photomask. A binary mask curve and a phase shift mask curve reflecting relationship between critical dimensions of the photomask and the original pattern are obtained. A critical value of the critical dimension is selected. For the binary mask curve, the portion with the critical dimension of the original pattern larger than the critical value is selected. In contrast, for the phase shift mask curve, the portion with the critical dimension of the original pattern smaller than the critical value is selected. These two portions are combined as an optical characteristic curve. The mixed mode photomask can thus be fabricated according to the optical characteristic curve.

Abstract: A method for producing an electrode of Ni/metal hydride alloy secondary cells. The electrode may be produced by mixing an active material with approximately 10-50 wt % of Cu powders, which can serve as a binder as well as a current collector, and cold-pressing the mixture at a pressure of 10 ton/cm. As the Cu-compacted electrode continues to experience the cycle of charge and discharge, the desolution-deposition of Cu is gradually produced. This desolution-deposition of Cu allows Cu to be deposited on the surface of the electrode comprising the hydrogen storage alloy, so that the electrode can be similar to a conventional Cu-electroless plated electrode in surface morphology. Consequently, the method of the invention can be an alternative for conventional electroless plating, which significantly improves the general functions of hydrogen storage alloy electrode, including low temperature dischargeability and high rate capability, without producing pollution of the environment.

Abstract: A method for manufacturing a dual damascene structure comprises the following steps. First, a first insulator having a first trench and a second trench therein is formed on a substrate. A first conductive line and a second conductive line are formed in the first trench and the second trench, respectively. A shielding layer is formed on the first conductive line. The upper part of the second conductive line is removed to form a third trench in the first insulator. The shielding layer is removed. A second insulator is formed on the first insulator and thoroughly fills the third trench. Part of the second insulator is removed until the first conductive line is exposed. A dielectric layer is formed on the second insulator and the first conductive line. The dielectric layer is patterned to form a fourth trench and to expose the first conductive line. Finally, a third conductive line is formed in the fourth trench to electrically connect the first conductive line.

Abstract: An optical proximity correction method for rectifying pattern on negative photoresist. Line pattern of integrated circuit is divided into L-shape regions or T-shaped regions. The L-shaped or T-shaped regions are further dissected into rectangular patches. Area of each rectangular patch is suitably reduced and reproduced onto a photomask. The photomask is used to form a corrected photoresist pattern.

Abstract: Circuit and method for generating a signal for use in locking a second signal on a first signal. The first and second signals have an associated frequency. A first beat note signal and a second beat note signal are generated from the first and second signals, respectively, when the frequencies of the first and second signals are not equal. The circuit includes a first and second flip-flop and detector circuitry. The first flip-flop is configured to receive the first and second beat note signals for generating a first state signal. The first flip-flop generates the first state signal by sampling the second beat note signal at a first periodic interval of the first beat note signal. The second flip-flop is configured to receive the first and second beat note signals for generating a second state signal. The second flip-flop generates the second state signal by sampling the second beat note signal at a second periodic interval of the first beat note signal.

Abstract: According to a broad aspect of a preferred embodiment of the invention, telephone calls, data and other multimedia information is routed through a hybrid network which includes transfer of information across the internet utilizing telephone routing information and internet protocol address information. The hybrid network includes an intelligent network solution which allows hybrid network service users to maintain the same experience and have access to the same information regardless of where or how they access the network. The solution avoids synchronicity management problems associated with replicating user data over a worldwide network.

Abstract: A damascene manufacturing process capable of forming borderless via. The process includes the steps of forming a first trench in a first dielectric layer above a substrate, and then forming a conductive line within the first trench. Thereafter, a portion of the conductive line is removed to form a second trench within the first dielectric layer directly above the conductive line. Next, material is deposited into the second trench to form a cap layer. Subsequently, a second dielectric layer is deposited over the first dielectric layer, and then the second dielectric layer is patterned to form a via opening that exposes the cap layer. Next, the cap layer is removed to form a cavity region that exposes the conductive line. Finally, a plug is formed within the cavity region and the via opening such that the plug is electrically connected with the conductive line.

Abstract: The teachings of the present invention aid a user in attaining an ergonomic position with respect to a remote object such as a display screen (e.g., VDT) or a manufacturing tool. To that end, various mechanisms which feedback to the viewer information related to position and orientation are taught. A first aspect incorporates a feedback mechanism into a display screen. The feedback mechanism could be formed in a variety of manners. In one embodiment, four lights are arranged such that a viewer in the proper orientation will perceive all four lights. However, as the viewer's orientation varies, one or more of the lights is concealed, thereby indicating to the user that the orientation is improper. In another embodiment, the cluster of lights is replaced with a cluster of four distinct pieces of diffraction grating. The diffraction grating could be such that the intensity of the reflected light varies as the viewer's orientation varies.

Abstract: A method of fabricating a dual trench capacitor with a horn region is provided. On a semiconductor substrate having at least a device isolation structure and a transistor thereon, wherein the transistor includes at least a gate and a source/drain region, an insulation layer with an opening exposing the source/drain region is formed. The opening is partly filled with a conductive plug, the plug having a surface level lower than a surface level of the insulation layer, so that a trench with a side wall of the insulation layer is formed on the plug within the opening. A conductive spacer is formed on the side wall with a horn shape. A part of the insulation layer which encompassing the conductive plug and the conductive spacer is removed, so that a dual trench structure which exposes outer side walls of the conductive spacer and the conductive plug, and a part of the insulation layer is formed.

Abstract: A method of fabricating a node contact window. A substrate having devices and a first dielectric layer is provided. Bit lines having spacer are formed on the first dielectric layer and a second is formed on the first dielectric layer. A hard material layer is then formed on the second dielectric layer. An opening is formed within the second dielectric layer to expose the spacer and the first dielectric layer. A polysilicon spacer is then formed on the sidewalls of the opening. A node contact window is formed by etching through the first dielectric layer to expose the substrate.

Abstract: There is disclosed a gear module comprising an output gear pivotally fitted to a base, a transmission gear rotated by a driving force from a driving motor to transmit the driving force to the output gear, a power actuating lever having a base end pivotally fitted to the base to be rotated around the base end; an actuated lever having a top end pivotally fitted to the transmission lever and a base end pivotally fitted to the base; and a connection bar connecting the top end of the power actuating lever and the top end of the actuated lever, the connection bar allowing the actuated lever to rotate in accordance with a rotation of the power actuating lever and allowing the transmission gear and the output gear to be engaged with each other, wherein the link axises of the power actuating lever and the connection bar form approximately a straight line when the transmission lever is engaged with the output gear.

Abstract: Disclosed is a biasing circuit for bringing a power FET to a substantial full enhancement. The biasing circuit includes: (a) a rail power voltage that is coupled to a drain terminal of the power field effect transistor; (b) a load being coupled between an other potential and a source terminal of the power field effect transistor; and (c) a micromachined DC/DC converter that is coupled between a gate terminal of the power field effect transistor and the rail power voltage. The micromachined DC/DC converter is configured to produce an enhanced voltage that is greater than the rail power voltage to the gate terminal of the power field effect transistor to achieve a substantial enhancement of the power field effect transistor.

Abstract: This invention provides charcoal cookers the ability to concentrate the fuel and to be able to remove the divider without disrupting the grill or food cooking on it while in operation. The invention further provides charcoal cookers with the ability to reposition a charcoal grill divider of this invention without disrupting the grill or food cooking on it while in operation.

Abstract: A method of optical proximity correction suitable for use in a mixed mode photomask. An original pattern is to be transferred from the mixed mode photomask. A binary mask curve and a phase shift mask curve reflecting relationship between critical dimensions of the photomask and the original pattern are obtained. A critical value of the critical dimension is selected. For the binary mask curve, the portion with the critical dimension of the original pattern larger than the critical value is selected. In contrast, for the phase shift mask curve, the portion with the critical dimension of the original pattern smaller than the critical value is selected. These two portions are combined as an optical characteristic curve. The mixed mode photomask can thus be fabricated according to the optical characteristic curve.